FinFET Fin Height Uniformity via Etch Protection Layer
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Solution Overview
Problem
Current FinFET fabrication techniques face challenges in achieving uniform fin height profiles due to recessing of the shallow trench isolation layer during gate oxide etch processes, leading to non-uniform fin profiles and increased effective oxide thickness, which results in undesired leakage paths.
Innovation Solution
The method involves forming a sacrificial gate structure with a sacrificial gate oxide layer and electrode layer, using an etch protection layer to prevent recessing of the isolation layer, and replacing the dummy gate structure with a metallic gate structure, ensuring uniform fin height profiles by preventing etching of the isolation layer during gate oxide removal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If gate oxide etch process is performed to remove dummy gate oxide, then gate structure preparation is improved, but isolation layer recessing occurs causing non-uniform fin heights
Solution Approach 1:
An etch protection layer is formed on the isolation layer before the gate oxide etch process. This preliminary protective action prevents the isolation layer from being etched during subsequent processing steps, thereby maintaining uniform fin heights while still allowing complete removal of the dummy gate oxide structure.
Solution Approach 2:
The etch protection layer acts as an intermediary between the etch chemistry and the isolation layer. It provides a sacrificial barrier that protects the isolation layer from direct exposure to the etch process, enabling the etch to proceed without causing isolation layer recessing or fin height non-uniformity.
2Productivity
If over-etch is used to remove thick thermal oxide layers, then oxide removal is improved, but STI oxide loss increases due to poor etch rate selectivity
Solution Approach 1:
The etch protection layer serves as an intermediary that prevents direct contact between the etch chemistry and the STI oxide layer. This allows aggressive etch conditions to be used for efficient oxide removal without causing STI oxide loss, as the protection layer absorbs the etching action.
Solution Approach 2:
The etch protection layer is applied beforehand to cushion and protect the STI oxide layer from the harsh etch environment. This prior protective measure enables the use of high-power etch processes for efficient oxide removal while preventing material loss from the isolation layer.
3Length of moving object
If fin profile thinning is applied to decrease active fin width, then device scaling is improved, but non-uniform fin profiles result due to additional STI layer recess
Solution Approach 1:
The etch protection layer is formed on the isolation layer before fin profile thinning operations. This preliminary protection ensures that when thinning processes are applied to reduce fin width, the isolation layer remains stable and does not recess, thereby maintaining uniform fin profiles throughout the device region.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in FinFET devices with uniform fin height profiles, reducing leakage paths and improving device performance by maintaining the isolation layer integrity during the gate oxide removal process.
Implementation Method 1
utilizing a first etch protection layer to prevent recessing of the isolation layer during the etching of the sacrificial gate oxide layer
Data Source
AI summary
Semiconductor devices and methods are provided to fabricate fin field-effect transistor (FinFET) devices having uniform fin height profiles. For example, uniformity of fin height profiles for FinFET devices is obtained by implementing a gate oxide removal process which is designed to prevent etching of an isolation layer (e.g., a shallow trench isolation layer) formed of an oxide material during removal of, e.g., sacrificial gate oxide layers of dummy gate structures during a replacement metal gate process.