FinFET Fabrication via Single EUV Patterning of CA and CB Contacts
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Solution Overview
Problem
The existing methods for fabricating FinFET integrated circuits require multiple separate patterning and etching steps for forming CA and CB local contact openings, which increase fabrication time, expense, and the likelihood of errors, making it economically unviable to replace conventional immersion lithography with EUV lithography.
Innovation Solution
The method involves using a single extreme ultraviolet (EUV) lithography patterning process to simultaneously form openings for both CA contacts to TS contact plugs and CB contacts to gate electrodes, reducing the number of masking and etching steps by using a silicon nitride capping layer and tungsten material as etch stops, allowing for the formation of metal fill materials in these openings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple separate patterning and etching steps are used to form CA and CB local contact openings, then the fabrication process can be completed with conventional immersion lithography, but the fabrication time and expense increase
Solution Approach 1:
The patent combines the formation of CA contact openings and CB contact openings into a single patterning step using EUV lithography. The method forms a unified pattern that simultaneously defines both CA contacts (to TS contact plugs) and CB contacts (to gate electrodes) in one exposure and development process, eliminating the need for separate masking and etching steps for each contact type.
Solution Approach 2:
The EUV lithography process is used to perform multiple functions that were previously required separate processes: it simultaneously patterns the CA contact openings, CB contact openings, and defines the boundaries between different contact regions. This multi-functional approach consolidates what were previously distinct patterning operations into a single universal patterning step.
2Reliability
If multiple separate patterning and etching steps are used to form CA and CB local contact openings, then the fabrication process can be completed with conventional immersion lithography, but the expense increases
Solution Approach 1:
The patent combines the formation of CA contact openings and CB contact openings into a single patterning step using EUV lithography. The method forms a unified pattern that simultaneously defines both CA contacts (to TS contact plugs) and CB contacts (to gate electrodes) in one exposure and development process, eliminating the need for separate masking and etching steps for each contact type.
Solution Approach 2:
The patent transitions from conventional immersion lithography to EUV lithography, changing the wavelength parameter of the light source used for patterning. This parameter change enables higher resolution and allows consolidation of multiple patterning steps into one, reducing the total number of process steps and associated costs despite the higher equipment investment.
3Productivity
If multiple separate patterning processes are used to form CA and CB contacts, then the fabrication can be completed, but the likelihood of errors increases
Solution Approach 1:
The patent combines the formation of CA contact openings and CB contact openings into a single patterning step using EUV lithography. The method forms a unified pattern that simultaneously defines both CA contacts (to TS contact plugs) and CB contacts (to gate electrodes) in one exposure and development process, eliminating the need for separate masking and etching steps for each contact type.
4Ease of manufacture
If conventional immersion lithography is used with multiple patterning steps, then the process is economically viable, but the number of steps increases fabrication complexity
Solution Approach 1:
The patent combines the formation of CA contact openings and CB contact openings into a single patterning step using EUV lithography. The method forms a unified pattern that simultaneously defines both CA contacts (to TS contact plugs) and CB contacts (to gate electrodes) in one exposure and development process, eliminating the need for separate masking and etching steps for each contact type.
Solution Approach 2:
The patent transitions from conventional immersion lithography to EUV lithography, changing the wavelength parameter of the light source used for patterning. This parameter change enables higher resolution and allows consolidation of multiple patterning steps into one, reducing the total number of process steps and associated costs despite the higher equipment investment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the fabrication process, reduces fabrication time and expense, and enhances the viability of using EUV lithography by consolidating five separate patterning processes into a single step, thereby improving the efficiency and reducing errors in the production of FinFET integrated circuits.
Implementation Method 1
a single extreme ultraviolet (EUV) lithography patterning process to simultaneously form openings for both CA contacts to TS contact plugs and CB contacts to gate electrodes
Implementation Method 2
using a silicon nitride capping layer and tungsten material as etch stops
Data Source
AI summary
A method for fabricating a finFET integrated circuit includes providing a finFET integrated circuit structure including a fin structure, a replacement metal gate structure having a silicon nitride cap disposed over and in contact with the fin structure, a contact structure including a tungsten material also disposed over and in contact with the fin structure, and an insulating layer disposed over the replacement metal gate structure and the contact structure. The method further includes forming a first opening in the insulating layer over the replacement gate structure and a second opening in the insulating layer over the contact structure. Forming the first and second openings includes exposing the FinFET integrated circuit structure to a single extreme ultraviolet lithography patterning. Still further, the method includes removing a portion of the silicon nitride material of the replacement metal gate structure and forming a metal fill material in the first and second openings.