FinFET Extra Fin Structure for Threshold and Leakage Tuning
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Solution Overview
Problem
As transistor dimensions continue to scale down, FinFETs face challenges in maintaining effective gate control and reducing short-channel effects, necessitating further improvements in design and fabrication.
Innovation Solution
The introduction of extra fin structures allows for the adjustment of the work function of the gate electrode by varying the spatial composition of the work function metal, and controlling the spacing, height, count, and shape of these extra fins to enhance filling of the work function metal, thereby tuning the threshold voltage and leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor dimensions are scaled down to increase device density, then productivity and cost are improved, but gate control effectiveness deteriorates and short-channel effects increase
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional FinFET structures with vertical fins extending from the substrate. This dimensional change increases the gate's control surface area over the channel without increasing the planar footprint, thereby maintaining effective gate control at scaled dimensions while increasing device density.
Solution Approach 2:
The gate electrode is positioned to surround the fin structure on three sides (top, front, and back surfaces), creating a nested configuration where the gate envelops the channel region. This multi-sided gating provides enhanced electrostatic control over the channel compared to conventional top-only gating, addressing the gate control deterioration at scaled dimensions.
2Reliability
If FinFET structures are used to improve gate control, then device performance is improved, but fabrication complexity increases
Solution Approach 1:
The fin structures are divided into multiple discrete fins arranged in arrays, with each fin serving as an independent channel region. This segmentation allows for modular fabrication processes and enables selective manipulation of individual fin parameters (width, height, spacing) to optimize performance while managing fabrication complexity.
Solution Approach 2:
The patent employs selective doping regions, varying fin heights, and differentiated material compositions in specific areas of the FinFET structure. For example, different doping concentrations are applied to source/drain regions versus channel regions, and fin heights may vary across the array to create devices with different threshold voltages, allowing localized optimization without complicating the overall fabrication process.
3Adaptability or versatility
If extra fin structures are added to tune device characteristics, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent utilizes extra fin structures with variable parameters including fin width, fin height, fin spacing, and doping concentration. By adjusting these parameters, the threshold voltage, leakage current, and contact resistance can be tuned independently. For instance, increasing fin height enhances gate control but may increase leakage, while adjusting fin spacing modifies the effective channel width and threshold voltage, providing multiple degrees of freedom for device optimization.
Solution Approach 2:
The extra fin structures are formed and configured during the initial fabrication sequence before final device assembly. The fins are created with predetermined dimensions and doping profiles through selective epitaxial growth and doping processes, establishing the device characteristics early in the manufacturing process. This preliminary configuration allows subsequent processing steps to focus on interconnect formation and device packaging, managing overall complexity.
Data Source
AI summary
Embodiments of the present disclosure provide a FinFET semiconductor including a first set of fin structures that are active, a source/drain (S/D) region in contact with the first set of fin structures, a second set of fin structures separated, via a shallow trench isolation (STI) feature, from the first set of fin structures, a contact etch stop layer (CESL) over the S/D region and over the second set of fin structures, and a gate over the first set of fin structures and over the second set of fin structures, the gate including a gate dielectric and a gate electrode over the gate dielectric. The second set of fin structures includes one or more non-active fin structures that are in contact with the CESL without being in contact with the S/D region.