FinFET Fault Injection via Defect-Describing Layers
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Solution Overview
Problem
Existing fault simulation methods for semiconductor devices, particularly finFETs, face challenges in accurately modeling and simulating defects in the complex three-dimensional gate dielectric and electrode structures, which are different from planar MOSFETs, leading to inefficiencies in identifying and addressing device failures.
Innovation Solution
The use of multi-gate transistors, specifically finFET devices, with a gate structure that includes a gate dielectric layer and electrode layer on multiple sides of the fin, along with a defect-describing layer system to accurately simulate and model faults at various locations on the fin, enabling precise identification of defects and their impact on transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If existing fault simulation methods are used for finFET devices, then planar MOSFET modeling approaches can be applied, but accuracy in modeling three-dimensional gate dielectric and electrode structures is insufficient
Solution Approach 1:
The gate structure is segmented into distinct components: gate dielectric layer, gate electrode layer, and fin structure. Each layer is assigned separate defect-describing layers that track defects independently, allowing accurate modeling of three-dimensional fault locations without being overwhelmed by overall structural complexity
Solution Approach 2:
The patent transitions from two-dimensional planar fault modeling to three-dimensional fault modeling by introducing vertical layering. Defects are described using three coordinates (x, y, z) corresponding to lateral position, vertical layer position, and depth within the layer, enabling accurate representation of faults in the three-dimensional finFET gate structure
2Reliability
If detailed geometric and location-specific fault modeling is implemented, then fault detection accuracy improves, but manufacturing complexity increases
Solution Approach 1:
The patent creates a virtual copy of the physical device structure through defect-describing layers that mirror the actual gate dielectric and gate electrode layers. This virtual model allows comprehensive fault simulation and detection without requiring changes to the physical manufacturing process, thereby maintaining ease of manufacture while improving fault detection accuracy
Solution Approach 2:
The defect-describing layers are prepared in advance during the simulation setup phase, defining all possible defect locations and characteristics before actual fault analysis. This preliminary structuring of fault modeling data enables efficient processing during manufacturing testing without adding complexity to the manufacturing operations themselves
Data Source
AI summary
Defect-describing (or “cut”) layer(s) for describing defects associated with different sides of a 3-dimensional (3D) structure enable fault modeling to determine the effect of position and location of defects on transistor performance. One or more defect-describing layers are used to identify the coordinates and sides of the 3D structures of the defects. The defect-describing layer(s) enables fault-modeling for 3D structures to understand the effects of faults on different locations, especially for defects associated with the fins of the finFET devices. Faults are injected to different locations and sides of fins and are modeled with different test vectors, test parameters and testing devices to identify detectable faults. The fault modeling would help identify the sources of defects and also improve layout design of finFET device structures.