FinFET Semiconductor Device with Field Plate for Low On-Resistance
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Solution Overview
Problem
MOS power transistors face challenges in achieving low switch-on resistance (Rdson) and high breakdown voltage characteristics, particularly in switching off states, where they need to withstand source-drain voltages of tens to hundreds of volts while conducting high currents with minimal voltage drop.
Innovation Solution
The semiconductor device design includes a transistor with a channel region and drift zone formed as ridges, where the channel region's width is less than or equal to twice the length of the depletion zone at the gate dielectric interface, and a field plate is used adjacent to the drift zone to control conductivity and enhance reverse voltage characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the channel width is reduced to suppress short channel effects, then breakdown voltage increases, but on-resistance increases
Solution Approach 1:
The patent transitions from a planar channel structure to a three-dimensional FinFET structure with vertical fins. This dimensional change increases the effective channel width without increasing the planar footprint, allowing simultaneous achievement of low on-resistance (through increased effective width) and high breakdown voltage (through maintained physical width control). The vertical fin structure provides greater surface area for current conduction while maintaining electrostatic control.
Solution Approach 2:
The channel region is segmented into multiple vertical fins rather than a single planar channel. This segmentation increases the total effective channel width by providing multiple conduction paths through the fins, thereby reducing on-resistance while each individual fin maintains sufficient width control for high breakdown voltage characteristics.
2Object-affected harmful factors
If lateral dimensions are increased to reduce on-resistance, then current conduction improves, but short channel effects worsen
Solution Approach 1:
The invention moves from two-dimensional planar geometry to three-dimensional vertical fins. The effective channel width is increased by adding vertical dimension (fin height and multiple fins) rather than increasing lateral dimensions. This maintains excellent electrostatic control and suppresses short channel effects while achieving low on-resistance through increased effective conduction area.
Solution Approach 2:
The channel structure combines multiple materials with different properties: silicon-germanium (SiGe) for the fin body providing mechanical strength and tailored electrical properties, silicon nitride for stress control, and silicon oxide for insulation. This composite structure enables optimized electrical characteristics with low on-resistance while maintaining dimensional control for short channel effect suppression.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design results in improved device characteristics by reducing on-resistance and suppressing short channel effects, allowing for efficient current control and increased breakdown voltage, thus enhancing the overall performance of MOS power transistors.
Implementation Method 1
a gate electrode adjacent to the channel region, the gate electrode configured to control a conductivity of a channel formed in the channel region
Implementation Method 2
the first ridge having a first width d1 with: d1≦2×ld, wherein ld denotes a length of a depletion zone formed at an interface between the first ridge and a gate dielectric
Data Source
AI summary
A semiconductor device comprises a transistor formed in a semiconductor substrate having a first main surface. The transistor includes a source region, a drain region, a channel region, a drift zone, and a gate electrode being adjacent to the channel region. The gate electrode is configured to control a conductivity of a channel formed in the channel region, the channel region and the drift zone are disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The channel region has a shape of a first ridge extending along the first direction, and the transistor includes a first field plate arranged adjacent to the drift zone.