FinFET Transistor Fin Back Biasing Method

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Solution Overview

Problem

FinFETs lack effective body biasing due to geometric limitations, which diminishes the body biasing effect typically seen in traditional transistor scaling, hindering the modulation of gate threshold voltage.

Innovation Solution

A method is introduced to form a FinFET with a shrunk portion as a body-biasing region, which is strategically positioned and dimensioned to apply a biasing voltage that influences the threshold voltage, allowing for effective body biasing by electrically connecting it to the source and drain regions, thereby enhancing the biasing effect.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If FinFET geometry is used for transistor scaling, then device density and manufacturing efficiency are improved, but body biasing capability is lost

Engineering Contradiction:
Improvedevice densityVSAvoidbody biasing capability
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The fin structure is segmented into multiple regions: a channel region adjacent to the gate and a biasing region at the distal end. This segmentation allows the biasing region to be independently controlled for applying body biasing voltage, thereby restoring body biasing capability in FinFET devices while maintaining the high density benefits of the FinFET geometry.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A biasing electrode is introduced as an intermediary component to apply body biasing voltage to the biasing region of the fin. This electrode acts as a mediator between the external biasing circuit and the fin structure, enabling effective body biasing control in FinFET devices without compromising their geometric advantages.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of manufacture

If traditional body biasing is applied to FinFET substrate, then manufacturing simplicity is maintained, but biasing effectiveness is diminished

Engineering Contradiction:
Improvebiasing implementation simplicityVSAvoidthreshold voltage modulation effectiveness
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

Instead of applying body biasing uniformly across the entire substrate, the invention applies biasing locally to the biasing region of the fin through a dedicated biasing electrode. This local quality approach ensures that the body biasing effect is concentrated where it is most effective—at the fin region adjacent to the channel—thereby improving threshold voltage modulation effectiveness while maintaining manufacturing simplicity.

Inventive Principle:
Principle #3Local quality

3Length of moving object

If fin geometry is made narrow and tall, then device scaling is achieved, but body effect is virtually eliminated

Engineering Contradiction:
Improvefin dimensionsVSAvoidbody effect presence
Core Design Contradiction:
Length of moving objectVSAdaptability or versatility

Solution Approach 1:

The invention extends the fin structure in the vertical dimension by creating a biasing region at the distal end of the fin, away from the gate. This dimensional extension provides an additional degree of freedom for applying body biasing voltage, thereby restoring the body effect in narrow and tall FinFET structures where traditional substrate biasing is ineffective.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS10868006B2FinFET transistor with fin back biasing
Publication Date: 2020.12.15 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US10868006B2 patent drawing
  • US10868006B2 patent drawing
  • US10868006B2 patent drawing

AI summary

A method of forming a semiconductor device includes forming a fin protruding from a substrate, the fin having a channel region, a source/drain (S/D) region, and a biasing region, wherein the channel region and the biasing region sandwich the S/D region. The method further includes trimming the biasing region to reduce a height of the biasing region and forming a gate structure engaging the channel region. The method also includes forming a conductive feature electrically coupling to the biasing region.