FinFET Fin Bulge Reduction via Segmented Isolation
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Solution Overview
Problem
Conventional FINFET processing techniques result in semiconductor fins with non-uniform widths, leading to degradation of gate control over the channel region due to fin bulges, which affects device performance.
Innovation Solution
The method involves forming semiconductor fins with a lower portion adjacent to the substrate and an upper portion extending vertically, where isolation regions are created with a narrower upper portion, allowing a conformal gate dielectric layer to fill spaces between the fin bulge area and isolation regions, ensuring the gate conductor layer is entirely above the fin bulge, thus maintaining uniform gate control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional processing techniques are used to form FINFET, then manufacturing is simpler and faster, but the semiconductor fin develops non-uniform width with fin bulge that degrades gate control
Solution Approach 1:
The isolation region is segmented into two distinct portions: a first isolation portion at the lower level and a second isolation portion at the upper level. This segmentation allows each portion to serve different functions - the first portion provides lateral isolation while the second portion provides vertical isolation, collectively preventing fin bulge without requiring complex fin structure modifications
Solution Approach 2:
The isolation structure transitions from a conventional single-level lateral isolation to a two-level isolation structure that extends vertically. The second isolation portion rises above the first isolation portion to address the fin bulge formation at the upper fin region, adding a vertical dimension to the isolation function
2Reliability
If conventional processing techniques are used, then manufacturing is easier, but gate control over the channel region is degraded due to fin bulge
Solution Approach 1:
The two-level isolation structure is formed before fin formation to pre-establish the isolation boundaries. This preliminary action defines the lateral and vertical constraints that prevent fin bulge during subsequent processing steps, ensuring proper gate control without requiring complex fin structure modifications later
Solution Approach 2:
The isolation regions act as intermediary structures that mediate between the substrate and the fin structure. By providing both lateral and vertical isolation, they prevent the harmful interaction between adjacent fins that causes bulge formation, thereby improving gate control through this intermediary isolation mechanism
3Reliability
If isolation regions are made taller to prevent fin bulge, then gate control is improved, but manufacturing precision requirements increase
Solution Approach 1:
Different portions of the isolation structure have different heights tailored to their specific functions. The first isolation portion has a height sufficient for lateral isolation, while the second isolation portion has increased height specifically at locations where vertical isolation is needed to prevent fin bulge. This localized height variation improves gate control where needed without uniformly increasing manufacturing precision requirements across the entire structure
Data Source
AI summary
Disclosed are a method of forming a fin-type field effect transistor (FINFET) and a FINFET structure. In the method, isolation regions are formed on opposing sides of a semiconductor fin. Each isolation region is shorter than the fin, has a lower isolation portion adjacent to a lower fin portion, and has an upper isolation portion that is narrower than the lower isolation portion and separated from a bottom section of an upper fin portion by a space. Surface oxidation of the upper fin portion thins the top section, but leaves the bottom section relatively wide. During gate formation, the gate dielectric layer fills the spaces between the bottom section of the upper fin portion and the adjacent isolation regions. Thus, the gate conductor layer is formed above any fin bulge area and degradation of gate control over the channel region due to a non-uniform fin width is minimized or avoided.