Fin-FET Fin-Cut Process Using Isolation Layer Masking
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Solution Overview
Problem
The scaling down of semiconductor devices increases manufacturing complexity, particularly in the fin cut process of Fin-FET devices, due to reduced overlay error margins and uniformity issues with fin spacers, leading to damage and residue defects during the annealing of isolation layers and fin structure bending.
Innovation Solution
A method for manufacturing Fin-FET devices using double or quadrup-patterning methodologies to form fin spacers, where the isolation layer acts as a mask for the fin-cut process, with controlled selective ratios to prevent damage to active fin structures and enhance process efficiency, and chemical mechanical planarization (CMP) to ensure uniformity and precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the fin cut process is performed with conventional methods, then the manufacturing process can be completed, but damage and residue defects occur on the fin structures due to reduced overlay error margins
Solution Approach 1:
The patent introduces an intermediary layer (mandrel or spacer) between the photolithography patterning and the final fin formation. This intermediary structure serves as a template that defines the fin positions and dimensions, allowing the actual fin cut to be performed with precise alignment relative to the isolation layer. The intermediary layer absorbs the overlay errors and provides a stable reference for subsequent etching steps, thereby preventing damage to the fin structures while maintaining manufacturing precision.
Solution Approach 2:
The patent performs preliminary patterning to form the intermediary layer (mandrel or spacer) before performing the actual fin cut. This preliminary action establishes the precise geometric constraints and positions for the fins in advance, allowing the subsequent etching process to proceed with well-defined parameters. By preparing the template structure beforehand, the process ensures that the fin cut occurs at the correct locations with proper dimensions, avoiding damage that would occur with direct conventional patterning.
2Ease of manufacture
If uniform fin spacers are used in the fin cut process, then the process is simpler, but fin structure bending occurs during annealing of the isolation layer
Solution Approach 1:
The patent applies different properties to different regions of the fin spacer structure. Specifically, the fin spacers are formed with varying heights or material compositions depending on their location - those adjacent to active fin structures have different characteristics than those in isolation regions. This local differentiation allows the spacers to serve multiple functions: providing structural support where needed while allowing controlled removal or deformation in other areas during annealing, thereby preventing fin structure bending while maintaining manufacturing feasibility.
Solution Approach 2:
The patent changes key parameters of the fin spacer structure, such as height, material composition, or cross-sectional shape, to optimize performance. By adjusting these parameters, the spacers can provide adequate mechanical support during processing to prevent bending, while also being removable or modifiable when no longer needed. The parameter changes enable the spacers to balance structural integrity with processability, resolving the contradiction between ease of manufacture and structural stability.
3Reliability
If the isolation layer is annealed to improve device performance, then electrical characteristics improve, but fin structure bending and damage occur
Solution Approach 1:
The patent introduces protective structures (such as sacrificial layers, reinforced spacers, or stress-compensating elements) before the annealing process. These cushioning elements are designed to absorb or distribute the thermal and mechanical stresses that occur during isolation layer annealing. By providing this protective buffer in advance, the actual fin structures are shielded from bending and damage, allowing the annealing process to proceed to improve device performance without compromising structural integrity.
Solution Approach 2:
The patent uses an intermediary protective layer or structure between the isolation layer and the fin structures during annealing. This intermediary element acts as a buffer that decouples the thermal expansion and stress effects of the isolation layer from the sensitive fin structures. The mediator absorbs the harmful effects of annealing while allowing the beneficial electrical characteristic improvements to occur, thereby resolving the contradiction between device performance enhancement and fin structure strength maintenance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the control and precision of the fin-cut process, reducing damage and residue defects, and stabilizes the performance of Fin-FET devices by maintaining the profile and critical dimension of active fin structures while allowing for varied fin heights, thus enhancing manufacturing efficiency.
Implementation Method 1
the isolation layer acts as a mask for the fin-cut process, with controlled selective ratios to prevent damage to active fin structures
Implementation Method 2
chemical mechanical planarization (CMP) to ensure uniformity and precision
Data Source
AI summary
A process of manufacturing a Fin-FET device, and the process includes following steps. An active fin structure and a dummy fin structure are formed from a substrate, and an isolation layer is covered over the active fin structure and the dummy fin structure. Then, the isolation layer above the dummy fin structure is removed, and the dummy fin structure is selectively etched, which a selective ratio of the dummy fin structure to the isolation layer is over 8.