FinFET Fin Formation Using Sequential Spacer Etching
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Solution Overview
Problem
The existing methods for forming fins in FinFETs often result in increased self-heating temperatures, leading to degradation in performance and reliability due to the need for finer patterns and steeper fin shapes, which can be challenging to achieve without compromising the semiconductor device's integrity.
Innovation Solution
A method involving the sequential deposition of hard mask layers and spacer formation on dummy gates, followed by selective removal of spacers to create fins with varying line widths on the same semiconductor substrate, allowing for the generation of both narrow and wide fins for nMOSFET and pMOSFET channels, respectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If double-patterning technology with spacer is used to form fine pattern fins, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent divides the fin formation process into multiple stages using sequential spacer formation. First spacers are formed and selectively removed, then second spacers are formed with different patterns. This segmentation allows independent optimization of narrow fins (using first spacer pattern) and wide fins (using second spacer pattern), achieving high manufacturing precision for different fin types without requiring a single complex patterning process.
Solution Approach 2:
The patent applies local quality by creating different fin geometries in different regions of the semiconductor substrate. Narrow fins are formed in first regions while wide fins are formed in second regions, allowing each region to have optimized fin dimensions tailored to specific transistor type requirements (nMOSFET vs pMOSFET), thereby improving overall device performance without compromising precision.
2Reliability
If fin shape is made steeper and taller to improve performance, then gate control is improved, but self-heating temperature increases
Solution Approach 1:
The patent implements local quality by providing different fin geometries for different transistor types. Narrow fins with optimized dimensions are created for nMOSFET channels while wider fins are created for pMOSFET channels. This allows each transistor type to have fins specifically optimized for its electrical characteristics, improving gate control for narrow fins while the wider fins provide better heat dissipation pathways, thereby balancing gate control improvement with self-heating management.
3Adaptability or versatility
If fins with different line widths are formed on the same wafer, then adaptability is improved, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
The patent uses segmentation by forming first spacers and second spacers through separate, sequential patterning processes. The first spacer formation process is optimized for creating narrow fins with high precision, while the second spacer formation process is optimized for creating wide fins. By segmenting the fin formation into these independent stages with selective spacer removal, the patent maintains manufacturing precision for each fin type while achieving adaptability to produce both narrow and wide fins on the same wafer.
Solution Approach 2:
The patent applies preliminary action by forming the first spacers and selectively removing them before forming the second spacers. This preliminary spacer formation and removal creates a prepared substrate state that enables subsequent wide fin formation without interfering with the previously formed narrow fins. This sequential preliminary action ensures that each fin type can be precisely formed according to its specific requirements while maintaining overall manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of FinFETs with fins of different line widths on the same wafer, improving heat dissipation and enhancing the performance and reliability of semiconductor devices by optimizing fin dimensions for specific transistor types.
Implementation Method 1
depositing a first hard mask layer on a first dummy gate and a second dummy gate
Implementation Method 2
depositing a first hard mask layer on a first dummy gate and a second dummy gate
Implementation Method 3
generating first spacers on the first dummy gate and second spacers on the second dummy gate by etching the first hard mask layer
Data Source
AI summary
A method of generating a fin of a FinFET includes depositing a first hard mask layer on or above a first dummy gate and a second dummy gate, generating first spacers and second spacers by etching the first hard mask layer, removing only the first spacers, depositing a second hard mask layer, generating third spacers and fourth spacers by etching the second hard mask layer, removing the first dummy gate and the second dummy gate, generating first fins using the third spacers, and generating second fins using the second spacers and the fourth spacers.