FinFET Fin Height Tuning With Recessed Isolation Under the Gate

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Solution Overview

Problem

The scaling down of FinFET technologies to smaller feature sizes poses challenges in precisely controlling fin profiles and dimensions, leading to issues such as fin collapse during fabrication, which affects transistor performance, reliability, and manufacturability.

Innovation Solution

A method is introduced to modify the fin structure by increasing its height under the gate structure for improved performance and structural support, involving the formation of a dummy gate, interlayer dielectric deposition, and selective etching to recess the isolation feature, allowing for a wider and shorter fin shape that maintains strength during processing while optimizing channel region dimensions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If fin height is increased to improve drive current and short-channel control, then transistor performance is improved, but fin structural stability deteriorates leading to fin collapse during fabrication

Engineering Contradiction:
Improvetransistor performanceVSAvoidfin structural stability
Core Design Contradiction:
ReliabilityVSStrength

Solution Approach 1:

A dummy gate structure is formed over the fin structure before the fin height is increased. This preliminary action provides structural support during subsequent processing steps that would otherwise cause fin collapse, enabling the fin height to be increased while maintaining fin stability throughout fabrication

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The isolation structure thickness is varied in the vertical dimension beneath the gate structure compared to regions outside the gate structure. This creates different fin heights in different horizontal locations, allowing optimized drive current and short-channel control in the channel region while maintaining structural stability through the dummy gate support

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If fin height is increased for optimized channel region, then drive current and short-channel control are improved, but manufacturing complexity increases due to additional processing steps

Engineering Contradiction:
Improvetransistor performanceVSAvoidfabrication process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The dummy gate structure serves multiple functions: it provides structural support during processing to prevent fin collapse, defines the channel region for selective isolation structure removal, and enables subsequent metal gate formation. This multi-functionality reduces overall manufacturing complexity despite the additional initial step

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The isolation structure is selectively removed only in the channel region beneath the gate structure, creating a localized fin height increase where it is most needed for transistor performance. This localized modification optimizes drive current and short-channel control without requiring global fin height increases that would complicate manufacturing

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20240405099A1Optimized fin height for finfet transistor and method of fabricating thereof
Publication Date: 2024.12.05 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240405099A1 patent drawing
  • US20240405099A1 patent drawing
  • US20240405099A1 patent drawing

AI summary

Method and devices that include a recessed isolation region in a trench region formed by the removal of a dummy gate structure. The recessed isolation region can allow a greater fin height in the channel region. A metal gate structure may be formed on the recessed isolation region and fin.