FinFET Fin Layout for Lower Leakage Without Speed Loss
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Solution Overview
Problem
FinFET devices with multiple fins suffer from increased current leakage and power consumption, while reducing the number of fins to mitigate these issues can lead to a reduction in speed.
Innovation Solution
The method involves reducing the number or height of fins in the gate structure of FinFET devices through etching processes, allowing for a non-integer number of fins to be maintained, which reduces current leakage and power consumption without compromising speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the number of fins in FinFET devices is increased to improve speed, then the speed is improved, but current leakage and power consumption increase
Solution Approach 1:
The gate structure is segmented into multiple fins, allowing selective removal of certain fins to achieve non-integer fin counts. This segmentation enables independent control of current leakage and speed characteristics by optimizing the number and configuration of remaining fins.
Solution Approach 2:
Different regions of the gate structure have different fin configurations. By removing specific fins from specific regions, the patent creates local variations in fin density that optimize both current leakage reduction and speed maintenance in different areas of the device.
2Loss of energy
If the number of fins in FinFET devices is reduced to decrease current leakage, then current leakage is reduced, but device speed decreases
Solution Approach 1:
The patent changes the parameter of fin count from integer values to non-integer values by selectively removing fins. This parameter change allows precise control over the balance between current leakage and speed, achieving optimal performance points that traditional integer-based fin counts cannot provide.
3Productivity
If the IC dimensions are reduced to increase production efficiency, then production efficiency is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent extracts unnecessary fins from the gate structure to achieve non-integer fin counts. This extraction simplifies the manufacturing process by reducing the number of etching steps and materials required, while maintaining high production efficiency through direct fin removal rather than complex patterning processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively alleviates current leakage and power consumption issues while maintaining the speed of FinFET devices, improving gate control reliability and reducing manufacturing complexity and costs.
Implementation Method 1
The method involves reducing the number or height of fins in the gate structure of FinFET devices through etching processes
Data Source
AI summary
A semiconductor device and a manufacturing method of the semiconductor device are provided. The semiconductor device includes a source region, a drain region, a channel region and a plurality of fins. The channel region is located between the source region and the drain region, and the fins pass through the source region, the drain region and the channel region, wherein a number of the fins located in the source region and the drain region and a number of the fins located in the channel region are not equal.