FinFET Fin Neck Profile Etching for Leakage Control
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to effectively form semiconductor fins with precise profiles to enhance electrical control and reduce leakage in FinFET devices, as existing methods struggle to achieve optimal fin dimensions and profiles for improved performance.
Innovation Solution
A method involving multiple etching cycles with specific etching processes and polymer layer formations is used to create semiconductor fins with neck portions and zig-zag sidewalls, which are designed to reduce electrical leakage and improve fin profiles, including the use of patterned mask and pad layers, and subsequent formation of insulators and gate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional single etching process is used, then manufacturing process is simple, but fin profile precision and dimensional control are insufficient
Solution Approach 1:
The etching process is divided into multiple sequential etching cycles, where each cycle includes forming polymer layers on opening surfaces, performing first etching process, and performing second etching process. This segmentation allows precise control of fin profile at different stages, achieving complex zig-zag sidewalls and neck portions with high dimensional accuracy
Solution Approach 2:
Polymer layers are formed on the surfaces of openings before each etching process to protect specific regions. This preliminary protective action enables selective etching of certain areas while preserving others, allowing precise control over fin profile development and dimensional accuracy throughout the multi-cycle process
2Reliability
If fin dimensions are reduced to improve electrical control, then gate control over channel is enhanced, but electrical leakage increases
Solution Approach 1:
The fin structure incorporates asymmetric neck portions with varying widths at different heights, and zig-zag sidewalls with different slopes on opposite sides. This asymmetric geometry creates regions of high electrical field concentration that improve gate control while the narrowed neck portions act as natural barriers to reduce off-state leakage current
Solution Approach 2:
The fin sidewalls are designed with curved zig-zag profiles rather than straight lines, creating smooth transitions and rounded corners. This curvature distribution optimizes electric field uniformity, reduces field concentration at sharp corners that would cause leakage, while maintaining overall compact dimensions for improved gate control
3Manufacturing precision
If multiple etching cycles with polymer layers are implemented, then fin profile precision is improved, but manufacturing time and process steps increase
Solution Approach 1:
The manufacturing process employs periodic repetition of the etching cycle, where each cycle consists of polymer layer formation followed by first and second etching processes. This periodic structured approach systematically builds the complex fin profile through controlled iterations, achieving high dimensional accuracy while maintaining process efficiency through rhythmical operation
Solution Approach 2:
Polymer layers are formed automatically on the opening surfaces through chemical reactions during the etching process itself, without requiring separate deposition equipment or additional material handling steps. This self-forming protective layer mechanism reduces process complexity and time while enabling precise fin profile control through the multi-cycle etching approach
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of semiconductor fins with precise dimensions and profiles that reduce electrical leakage and enhance the performance of FinFET devices by optimizing fin shapes and reducing Ioff current.
Implementation Method 1
performing a first etching process on the plurality of openings; performing a second etching process on the plurality of openings
Implementation Method 2
forming a plurality of polymer layers on surfaces of the openings
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, at least one semiconductor fin and a gate stack. The semiconductor fin is disposed on the semiconductor substrate. The semiconductor fin includes a first portion, a second portion and a first neck portion between the first portion and the second portion. A width of the first portion decreases as the first portion becomes closer to the first neck portion, and a width of the second portion increases as the second portion becomes closer to a bottom surface of the semiconductor substrate. The gate stack partially covers the semiconductor fin.