FinFET Fin Formation Layout to Avoid Pattern Loading Effects
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Solution Overview
Problem
Conventional FinFET manufacturing processes face challenges due to pattern loading effects caused by dense and sparse pattern regions in hard masks, leading to variations in fin formation and adverse effects on FinFET performance as integrated circuits scale down.
Innovation Solution
A method is developed to form semiconductor fins by using a series of layers and patterning steps, including the use of spacer layers and multiple etching processes to create uniform fin structures, avoiding the pattern loading effect by patterning after fin formation, and utilizing STI regions with non-flat bottom surfaces to ensure consistent fin dimensions and profiles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If hard masks with pattern-dense and pattern-sparse regions are used for etching fins, then fin formation is achieved, but pattern loading effects cause variations in fin dimensions and profiles
Solution Approach 1:
The patent segments the fin formation process into multiple steps: first forming fins in pattern-sparse regions, then forming fins in pattern-dense regions using a second etching process. This segmentation allows independent optimization of etching conditions for each region type, eliminating pattern loading effects and ensuring uniform fin dimensions across the substrate.
Solution Approach 2:
The patent performs preliminary etching of fins in pattern-sparse regions before addressing pattern-dense regions. By completing the etching process in easier-to-etch regions first, the method establishes a baseline for fin formation and allows subsequent adjustment of etching parameters for pattern-dense regions to achieve matching fin characteristics.
2Productivity
If integrated circuits are scaled down with thinner fins and greater aspect ratios, then higher drive currents with smaller dimensions are achieved, but process variations in fin formation increase
Solution Approach 1:
The patent employs dynamic process adjustment by using two different etching processes with tailored parameters for different pattern densities. The etching conditions are dynamically adapted to the local pattern characteristics, allowing precise control of fin formation even as fin thickness decreases and aspect ratios increase during scaling.
Solution Approach 2:
The patent changes etching parameters (such as etch chemistry, power, pressure, or temperature) between the first and second etching processes to compensate for pattern loading effects. By adjusting these parameters based on the specific pattern density being processed, the method maintains consistent fin dimensions and profiles despite circuit scaling challenges.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of consistent semiconductor fins with reduced process variations, improving FinFET performance by minimizing the pattern loading effect and ensuring uniformity in fin dimensions and profiles, thus enhancing the reliability of FinFETs in scaled-down integrated circuits.
Implementation Method 1
The hard masks are then used as etching masks to etch the underlying semiconductor substrates
Implementation Method 2
A first layer is formed over the hard masks and the second layer is formed over the first layer
Data Source
AI summary
A method includes forming a patterned etching mask, which includes a plurality of strips, and etching a semiconductor substrate underlying the patterned etching mask to form a first plurality of semiconductor fins and a second plurality of semiconductor fins. The patterned etching mask is used as an etching mask in the etching. The method further includes etching the second plurality of semiconductor fins without etching the first plurality of semiconductor fins. An isolation region is then formed, and the first plurality of semiconductor fins has top portions protruding higher than a top surface of the isolation region.