FinFET Fin Structure Profile for Sub-10 Nm CD Control
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Solution Overview
Problem
As semiconductor technology advances to sub 10-15 nm nodes, there are challenges in achieving precise critical dimension control and defect-free fin formation in three-dimensional designs like FinFETs, requiring improved fabrication processes.
Innovation Solution
A method involving double-patterning or multi-patterning photolithography processes is used to create fin structures, employing sacrificial layers, spacers, and etching stages with specific gas combinations to form uniform and defect-free fin structures, utilizing etching apparatuses with controlled plasma environments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional single-patterning photolithography is used, then the fabrication process is simple, but the critical dimension control precision is insufficient for sub 10-15 nm nodes
Solution Approach 1:
The patent applies segmentation by dividing the single patterning step into multiple patterning steps (e.g., self-aligned double patterning). First, a mandrel pattern is formed, then spacers are deposited and patterned to create additional features. This multi-stage approach enables sub-10nm critical dimension control that cannot be achieved with conventional single-patterning, while the self-aligned nature keeps the process complexity manageable.
2Productivity
If transistor dimensions are scaled down to sub 10-15 nm, then device density and performance are improved, but fin formation defects and damage increase
Solution Approach 1:
The patent employs preliminary action through multiple preparatory steps before final fin formation. Self-aligned spacer deposition and mandrel removal are performed in advance to define precise fin locations and dimensions. This preliminary structuring ensures that when fins are formed at sub-10nm scales, they are defect-free and properly aligned, enabling high device density without compromising reliability.
Solution Approach 2:
The patent uses intermediary structures (mandrels and spacers) to mediate the fin formation process. These intermediary elements serve as templates that guide the self-aligned etching process, ensuring precise fin positioning and dimensions. The intermediary structures are temporarily present during fabrication and are removed after serving their guiding function, enabling defect-free fin formation at scaled dimensions.
3Manufacturing precision
If multi-patterning processes are used, then critical dimension precision is improved, but fabrication time and process steps increase
Solution Approach 1:
The patent merges multiple patterning operations into a self-aligned process sequence. The spacer deposition and pattern transfer steps are combined in a way that automatically aligns features without requiring separate alignment operations. This merging of steps achieves multi-patterning precision while reducing the total time compared to conventional multi-step lithography processes that require multiple alignments.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method ensures precise control of critical dimensions and defect-free fin formation, enhancing the uniformity and integrity of FinFET structures, thereby improving device performance and reliability.
Implementation Method 1
an etching apparatus for patterning the substrate to form the fin structures
Implementation Method 2
A method involving double-patterning or multi-patterning photolithography processes is used to create fin structures
Data Source
AI summary
A semiconductor device and a method of fabricating a semiconductor device are provided herein. The semiconductor device includes a substrate; a fin structure arranged on the substrate and including a ridge portion and a bottom portion between the ridge portion and the substrate, wherein the ridge portion comprises a channel region and a fin region between the channel region and the bottom portion, a critical dimension of the bottom portion in a cross-fin direction is gradually increased toward the substrate to twice or more of a critical dimension of the channel region in the cross-fin direction; a metal gate structure disposed on the fin structure extending the cross-fin direction; and an epitaxy region disposed beside the metal gate structure in a lengthwise direction of the fin structure and connected to the fin structure.