FinFET Fin Replacement via Selective Dry Etching and Nitride Liners

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Solution Overview

Problem

Current FinFET integration processes result in costly wide and deep trenches during fin removal and require additional chemical mechanical polishing (CMP) on non-uniform wafers, leaving behind topography that complicates gate formation.

Innovation Solution

A method involving the formation of silicon fins with an oxide between them, followed by a nitride liner deposition, selective dry etching of unnecessary fins, and subsequent nitride liner removal to create a planar surface, avoiding trench etching and filling costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If a dry etch process is used to remove unnecessary fins, then fin removal is achieved, but wide and deep trenches are created that are costly to fill

Engineering Contradiction:
Improvefin removal processVSAvoidtrench volume
Core Design Contradiction:
Ease of manufactureVSVolume of stationary object

Solution Approach 1:

A sacrificial oxide layer is introduced as an intermediary material between the silicon fins. This oxide layer allows for selective fin removal through etch processes that target the oxide rather than creating deep trenches in the substrate, thereby reducing the volume of material that needs to be filled later

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The etch selectivity parameters are optimized to etch the oxide layer preferentially over the silicon fins and surrounding materials. By controlling etch chemistry and conditions, the process removes fins through the oxide sacrificial layer without creating excessive trench depth, thus reducing trench filling costs

Inventive Principle:
Principle #35Parameter changes

2Manufacturing precision

If an additional CMP step is performed on a non-uniform wafer, then planarization is achieved, but the process complexity increases and topography must be accounted for during gate formation

Engineering Contradiction:
Improvewafer planarityVSAvoidprocess steps
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The sacrificial oxide layer is formed and patterned before fin removal, establishing a pre-defined planarization pathway. This preliminary structure guides subsequent etching and removal steps to naturally achieve planarity without requiring additional CMP processing

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The unnecessary fins are selectively removed through the sacrificial oxide layer, extracting only the required fin structures while leaving the surrounding area intact. This selective extraction maintains wafer uniformity and eliminates the need for CMP-based planarization

Inventive Principle:
Principle #2Taking out (Extraction)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively removes unnecessary fins without the need for costly trench etching and filling, achieving a planar wafer surface suitable for gate formation, enhancing the efficiency of FinFET integration processes.

Implementation Method 1

forming a first nitride liner on an upper surface of the first plurality of silicon fins and the oxide therebetween

Methodology Applied
Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Implementation Method 2

forming the first nitride liner from furnace nitride or plasma-enhanced chemical vapor deposition (PECVD) nitride

Methodology Applied
Scientific EffectChemical Vapour Deposition: Chemical Vapour Deposition

Implementation Method 3

etching the second plurality of silicon fins by dry etching the fins

Methodology Applied
Scientific EffectPlasma: Plasma

Implementation Method 4

dry etching the nitride layer on the second plurality of silicon fins and on the oxide therebetween

Methodology Applied
Scientific EffectChemical Vapour Deposition: Chemical Vapour Deposition

Implementation Method 5

isotropically wet etching any stringers in the trenches following the dry etching of the silicon fins

Methodology Applied
Scientific EffectIsotropic Etching:

Implementation Method 6

recessing the oxide by atomic layer etching or wet etching the oxide

Methodology Applied
Scientific EffectAtomic Layer Etching:

Data Source

PatentUS9054212B2Fin etch and Fin replacement for FinFET integration
Publication Date: 2015.06.09 GLOBALFOUNDRIES US INC
  • US9054212B2 patent drawing
  • US9054212B2 patent drawing
  • US9054212B2 patent drawing

AI summary

A method and device are provided for etching and replacing silicon fins in connection with a FinFET integration process. Embodiments include providing a first plurality and a second plurality of silicon fins on a silicon wafer with an oxide between adjacent silicon fins; forming a first nitride liner on an upper surface of the first plurality of silicon fins and the oxide therebetween; etching the second plurality of silicon fins, forming trenches; removing the first nitride liner; depositing a second nitride liner on an upper surface of the first plurality of silicon fins and the oxide therebetween and in the trenches; removing the second nitride liner down to the upper surface of the first plurality of silicon fins; and recessing the oxide.