FinFET Fin Structure Formation via Selective Etching
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Solution Overview
Problem
Current methods for manufacturing FinFET structures face challenges in achieving high aspect ratio fin structures due to limitations in patterning and lithography processes, particularly for sub-10 nm nodes, leading to poor device performance and reduced throughput.
Innovation Solution
The method involves forming superlattice structures through selective etching and deposition processes, using mandrel structures and conformal epitaxial deposition of materials to create FinFET structures, which simplifies patterning and enables the transition from silicon to III-V materials while maintaining crystal lattice orientations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
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If conventional multiple patterning processes (SADP, SAQP) are used to form sub-10 nm node FinFET structures, then the fin structure pitch size can be reduced, but the patterning reliability deteriorates and process complexity increases
Solution Approach 1:
The patent introduces sacrificial mandrel structures as intermediary elements that enable the formation of sub-10 nm pitch fins through a simplified two-step process. The mandrels serve as temporary placeholders that guide the subsequent deposition and release steps, achieving high precision patterning without the complexity of multiple lithography steps. This intermediary approach transforms a complex direct patterning problem into a sequence of simpler, more reliable processes.
Solution Approach 2:
The patent performs preliminary formation of mandrel structures before the actual fin formation process. By pre-establishing the pitch definition through mandrels and using conformal deposition to create spacers, the method determines the final fin pitch early in the process sequence. This preliminary action allows subsequent steps to focus on material formation rather than precision patterning, improving both reliability and simplifying the overall process.
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If litho-etch-litho-etch (LELE) processes with 193 nm immersion photolithography are used, then sub-10 nm node FinFET structures can be formed, but line width roughness (LWR) of the resist increases leading to poor device performance
Solution Approach 1:
The patent uses sacrificial mandrel structures as intermediaries that define the pitch without requiring high-LWR resists. The mandrels serve as precise templates, and the conformal spacer deposition transfers this precision to the final fin structures. This approach decouples the pitch definition function from the resist material, eliminating the LWR problem inherent in direct lithography approaches.
Solution Approach 2:
The patent replaces the lithography-based mechanical patterning system with a deposition-based spacer formation system. Instead of relying on resist patterns that suffer from LWR, the method uses conformal atomic layer deposition to create spacers with atomic-level precision. This substitution of the patterning mechanism eliminates the source of line width roughness while maintaining sub-10 nm pitch control.
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If multiple patterning processes are used to achieve sub-10 nm pitch, then the fin structure density increases, but the manufacturing throughput decreases due to increased process time
Solution Approach 1:
The patent merges multiple patterning operations into a single integrated process sequence. The mandrel formation, spacer deposition, and fin formation steps are combined into a unified flow that achieves sub-10 nm pitch in one processing cycle rather than requiring separate lithography-etch cycles. This merging of operations maintains high fin density while improving throughput by eliminating redundant process steps.
Solution Approach 2:
The patent maintains continuous useful action throughout the fin formation process. The conformal deposition steps continuously build material on the mandrels and previous layers without interruption, and the release steps continuously transform the structure from mandrel-based to fin-based. This continuous transformation approach eliminates idle time between patterning and formation steps, maximizing manufacturing throughput while maintaining sub-10 nm precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the efficient formation of sub-10 nm node FinFET structures with improved performance by reducing the need for multiple patterning processes and minimizing crystallographic dislocations, thereby enhancing device performance and manufacturing efficiency.
Implementation Method 1
epitaxially depositing a first silicon germanium material layer on a silicon substrate having one or more silicon mandrel structures formed thereon and epitaxially depositing a first silicon layer on the first silicon germanium layer
Data Source
AI summary
Methods and apparatus for forming FinFET structures are provided. Selective etching and deposition processes described herein may provide for FinFET manufacturing without the utilization of multiple patterning processes. Embodiments described herein also provide for fin material manufacturing methods for transitioning from silicon to III-V materials while maintaining acceptable crystal lattice orientations of the various materials utilized. Further embodiments provide etching apparatus which may be utilized to perform the methods described herein.