FinFET Fin Dimensional Control via Selective Dummy Gate Removal
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Solution Overview
Problem
Current methods for fabricating semiconductor ICs with FINFET type transistors lack the flexibility to form dimensionally different fins, which limits the ability to achieve multiple threshold voltages and varying transistor performance.
Innovation Solution
The method involves etching trenches into a silicon substrate, filling them with insulating material to form silicon fins, creating dummy gate structures, and modifying the fins by removing upper portions and depositing high-k dielectric and work function determining gate electrode materials to achieve dimensionally distinct active fins, allowing for different transistor channel widths and threshold voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If current fabrication methods are used to form FINFET transistors, then transistor density is increased through size reduction, but flexibility to form dimensionally different fins with multiple threshold voltages is lost
Solution Approach 1:
The fabrication process is segmented into distinct stages: initial trench etching and insulation, dummy gate formation, selective fin removal, and final gate deposition. This segmentation allows different fin dimensions to be created through controlled removal of specific fins at different stages, providing flexibility without overwhelming process complexity
Solution Approach 2:
Dummy gate structures are formed preliminarily over all fins before selective removal. This preliminary action establishes a framework that guides subsequent selective fin removal processes, enabling precise dimensional control while maintaining process organization and reducing overall complexity
2Adaptability or versatility
If uniform fin dimensions are used across all transistors, then fabrication process is simplified, but ability to achieve multiple threshold voltages and varying transistor performance is limited
Solution Approach 1:
Different fin dimensions are created by applying local quality principles: specific fins are selectively removed based on their position and intended function. This allows certain regions to have different fin heights or widths tailored to specific threshold voltage requirements, achieving multiple transistor performance levels with precise dimensional control
Solution Approach 2:
The invention utilizes parameter changes by controlling which fins are removed and to what extent. By varying the removal depth, timing, and selectivity of fin removal processes, different fin dimensional parameters are achieved across the device array, enabling multiple threshold voltages while maintaining manufacturing precision through controlled parameter variation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of FINFETs with different transistor channel widths, resulting in multiple threshold voltages and varying transistor performance, enhancing the flexibility and efficiency of semiconductor device design.
Implementation Method 1
etching a plurality of trenches into a silicon substrate
Implementation Method 2
A first quantity of high-k dielectric material and a second quantity of work function determining gate electrode material are deposited overlying the first altered active fins portion
Data Source
AI summary
Methods are provided for forming semiconductor devices. One method includes etching trenches into a silicon substrate and filling the trenches with an insulating material to delineate a plurality of spaced apart silicon fins. Dummy gate structures are formed, which includes a first dummy gate structure, that overlie and are transverse to the fins. A back fill material is filled between the dummy gate structures. The first dummy gate structure and an upper portion of the insulating material are removed to expose an active fins portion of the fins. The active fins portion is dimensionally modified to form an altered active fins portion. A high-k dielectric material and a work function determining gate electrode material are deposited overlying the altered active fins portion.