FinFET Device Fin Structure Shape Control via Mandrel Templates
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Solution Overview
Problem
Existing FinFET devices and fabrication methods face challenges in achieving optimal fin structure shape and critical dimension control, particularly in scaling down to smaller geometries, which affects the complexity and efficiency of semiconductor integrated circuit manufacturing.
Innovation Solution
A method for fabricating FinFET devices involves forming fin structures with precise control over their width and shape, including depositing semiconductor material layers and etching processes to create a vertical profile, allowing for the formation of various fin shapes such as keystone, necking, and Ω-shapes, and integrating high-k/metal gate stacks for improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional planar transistors are used, then manufacturing process is simpler, but device performance and scalability are limited
Solution Approach 1:
The patent transitions from planar (2D) transistor structures to three-dimensional FinFET structures with vertical fins extending from the substrate. This dimensional change increases the effective channel area and gate control over the current path, significantly improving device performance and scalability without proportionally increasing manufacturing complexity
2Productivity
If geometry size is scaled down to increase functional density, then production efficiency increases, but manufacturing precision requirements become more stringent
Solution Approach 1:
The patent segments the transistor channel into multiple vertical fins rather than using a single planar channel. This segmentation allows each fin to be independently formed with controlled dimensions, enabling better critical dimension control at scaled geometries while increasing total functional density and production efficiency
Solution Approach 2:
The patent employs preliminary patterning steps including mandrel formation and spacer deposition before final fin structure creation. These preliminary actions establish precise dimensional templates that guide subsequent etching processes, ensuring critical dimension control is achieved before the actual fin formation occurs
3Reliability
If fin structure width is reduced to improve device performance, then device performance improves, but control over fin shape and dimensions becomes more difficult
Solution Approach 1:
The patent introduces intermediary structures including sacrificial mandrels and conformal spacers that act as templates for fin formation. These intermediaries provide precise dimensional control during fabrication, enabling the creation of narrow fins with well-defined shapes and dimensions while maintaining manufacturability
Solution Approach 2:
The patent utilizes parameter changes in the deposition and etching processes, including conformal deposition thickness control and anisotropic etching conditions, to precisely define fin width and shape. By adjusting process parameters such as deposition rate, temperature, and etch chemistry, the fin structures achieve the desired narrow dimensions with excellent shape control
Data Source
AI summary
A semiconductor device includes a first fin structure extending from a semiconductor substrate. A second fin structure is disposed over the first fin structure. The second fin structure includes a first layer including a first semiconductor material. The second fin structure further includes a second layer including a second semiconductor material disposed over the first layer. The second layer has a vertical sidewall. The second semiconductor material is different from the first semiconductor material. A gate structure is disposed over the semiconductor substrate and wraps around the first and second layers of the second fin structure.