FinFET Fin Implantation for STI Height and Edge Control

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Solution Overview

Problem

As semiconductor devices continue to scale down, FinFETs face challenges such as fin height loss, wiggle effect, and increased line edge roughness during the formation of shallow trench isolation (STI) regions, which affect device performance.

Innovation Solution

The implementation of an implantation process to form a silicon-rich region in the semiconductor fins, which enhances the Young's modulus and reduces the wiggle effect, thereby improving the fin's etching selectivity and line edge roughness.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If standard STI formation process is used, then isolation regions are formed, but fin height loss and wiggle effect occur

Engineering Contradiction:
Improvefin height controlVSAvoiddevice performance consistency
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent applies preliminary action by forming a protective layer on the fin structure before the STI formation process. This protective layer is deposited in advance to prevent fin height loss and reduce the wiggle effect during subsequent etching and isolation formation steps, thereby maintaining fin integrity and improving manufacturing precision.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent employs parameter changes by modifying the physical and chemical properties of the fin structure through controlled deposition and treatment processes. By adjusting parameters such as layer composition, thickness, and material properties, the fin structure becomes more resistant to height loss and deformation during STI formation, ensuring both precision and reliability.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If fin size is reduced for scaling, then device density increases, but line edge roughness increases

Engineering Contradiction:
Improvedevice densityVSAvoidline edge roughness
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent applies local quality by providing enhanced protection specifically at the fin edges and critical regions during STI formation. The protective layer is strategically positioned and configured to offer superior edge definition and reduce line edge roughness precisely where needed, while allowing the overall device density to increase through continued scaling.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces fin height loss, minimizes the wiggle effect, and enhances line edge roughness, resulting in improved performance and consistency of FinFETs during the STI formation process.

Implementation Method 1

performing an implantation process on the first fin to form an implant region near the top surface of the first fin

Methodology Applied
Scientific EffectIon Implantation: Ion Implantation

Data Source

PatentUS12310093B2Semiconductor device and manufacturing method thereof
Publication Date: 2025.05.20 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12310093B2 patent drawing
  • US12310093B2 patent drawing
  • US12310093B2 patent drawing

AI summary

A method of manufacturing a semiconductor device is provided. The method comprises the following steps of forming a first semiconductor layer over a substrate, the first semiconductor layer comprising a first semiconductor material; etching the first semiconductor layer to form a first recess; forming a second semiconductor layer in the first recess, the second semiconductor layer comprising a second semiconductor material different from the first semiconductor material; etching the first semiconductor layer and the second semiconductor layer to form a first fin comprising the second semiconductor layer and the first semiconductor layer; forming an insulation material over the substrate, wherein a top surface of the insulation material is flush with a top surface of the first fin; performing an implantation process on the first fin to form an implant region near the top surface of the first fin; and partially removing the insulation material to form shallow trench isolation regions, wherein the first fin is sandwiched by two adjacent shallow trench isolation regions.