FinFET Fin Reshaping for Strain Control and Threshold Uniformity
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Solution Overview
Problem
Current semiconductor technologies face challenges in controlling strain in FinFET devices' channels and reducing fin wiggle/bend effects, which affect device performance and uniformity of threshold voltage along fin heights.
Innovation Solution
The method involves forming semiconductor strips over a substrate, creating isolation regions, and performing multiple etch processes to reshape the strips into fins with controlled geometries, ensuring uniform Ge concentration and reducing fin widths as they extend from isolation regions, thereby controlling strain and eliminating fin wiggle/bend effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple etch processes are performed to reduce fin widths and control geometry, then manufacturing precision of fin structure is improved, but device complexity increases
Solution Approach 1:
The etch process is divided into multiple sequential stages (first etch process, second etch process, third etch process), each targeting specific geometric features of the fin structure. The first etch reduces overall fin width, the second etch creates tapered portions, and the third etch forms notches at fin bottoms, allowing precise control of fin geometry through segmented processing steps
Solution Approach 2:
Mandrel structures and spacer structures are formed beforehand to serve as etch masks that define the desired fin geometry. The mandrel is formed first, then spacers are deposited on its sidewalls, creating a preliminary template that guides the subsequent etch processes to achieve the target fin shape with controlled dimensions
2Reliability
If fin widths are reduced as they extend from isolation regions, then strain control in channel is improved, but manufacturing precision requirements increase
Solution Approach 1:
The fin structure is designed with non-uniform width characteristics: wider portions at the top for current conduction, tapered middle sections for strain control, and narrower notched portions at the bottom. This local variation in fin width is achieved through selective etching that creates different geometric features at different vertical positions, optimizing both electrical performance and mechanical stability
Solution Approach 2:
The fin structure incorporates curved and tapered geometries rather than straight vertical walls. The sidewalls are formed with controlled angles and curvature through the etch processes, creating a smooth transition from wider top portions to narrower bottom portions, which helps distribute stress uniformly and prevents sharp corners that could cause stress concentration
3Manufacturing precision
If Ge concentration is maintained uniformly in fins, then threshold voltage uniformity is improved, but manufacturing complexity increases
Solution Approach 1:
Multiple material layers containing germanium (SiGe source/drain regions, Ge-rich spacer material, Ge-containing mandrel) are combined in a single fin structure. The germanium is distributed throughout the structure through these merged components, ensuring uniform Ge concentration and threshold voltage across the channel while achieving the desired fin geometry through the integrated structure
Solution Approach 2:
The germanium concentration is varied in different regions during deposition: high Ge content in spacer and mandrel materials, graded Ge content in SiGe source/drain regions. This parameter variation in material composition is used to control the final Ge distribution uniformly in the fin channel, achieving threshold voltage uniformity through controlled compositional changes
Data Source
AI summary
A FinFET device and a method of forming the same are provided. The method includes forming semiconductor strips over a substrate. Isolation regions are formed over the substrate and between adjacent semiconductor strips. A first recess process is performed on the isolation regions to expose first portions of the semiconductor strips. The first portions of the semiconductor strips are reshaped to form reshaped first portions of the semiconductor strips. A second recess process is performed on the isolation regions to expose second portions of the semiconductor strips below the reshaped first portions of the semiconductor strips. The second portions of the semiconductor strips are reshaped to form reshaped second portions of the semiconductor strips. The reshaped first portions of the semiconductor strips and the reshaped second portions of the semiconductor strips form fins. The fins extend away from topmost surfaces of the isolation regions.