FinFET Fin Thinning Feedback for Precise Width Control
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Solution Overview
Problem
In the manufacturing of Fin Field-Effect Transistors (FinFETs), existing processes face challenges in achieving precise control over fin thickness and width variation, which affects gate control and current density, particularly as transistors are scaled down.
Innovation Solution
A method involving the measurement of semiconductor fin widths, generation of customized etching recipes, and iterative thinning processes to achieve target widths, using etching chemicals with selective rates to minimize variation and improve gate control, including the use of amine derivatives and controlled etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fin formation processes are used, then fins are formed by etching and STI recessing, but precise control over fin thickness and width variation is difficult to achieve
Solution Approach 1:
The patent applies preliminary action by forming a dummy gate stack before the fin thinning process. This dummy gate stack serves as a protective structure that defines the fin width during subsequent etching operations. The gate spacer is formed first, then the dummy gate stack is deposited, and only after the fin thinning is complete is the dummy gate stack removed. This preliminary structuring enables precise fin width control while simplifying the overall process by providing a self-aligned reference for the thinning operation.
Solution Approach 2:
The patent implements feedback through an iterative measurement and adjustment process. Fin widths are measured after formation, and based on these measurements, the fin thinning process is adjusted to achieve target widths. The process includes: measuring fin widths, comparing with target widths, adjusting etching parameters based on the comparison, and re-measuring to verify. This closed-loop feedback system ensures precise fin width control while adapting to actual process variations.
2Speed
If fin dimensions are reduced to increase drive current, then transistor speed improves, but gate control and current density become harder to control
Solution Approach 1:
The dummy gate stack is formed in advance before the fin thinning process, creating a protective cap that prevents over-etching during the thinning operation. This preliminary structure ensures that even as fins are thinned to increase drive current, the fin width is precisely controlled by the gate spacer dimension, maintaining gate control and current density consistency.
Solution Approach 2:
The iterative measurement and adjustment process provides real-time feedback on fin dimensions during scaling. Fin widths are measured, compared to targets, and the thinning process is adjusted accordingly. This feedback mechanism ensures that as fin dimensions are reduced to increase speed, the fin thickness and width remain precisely controlled, maintaining optimal gate control and current density.
3Manufacturing precision
If iterative measurement and adjustment processes are implemented, then fin width precision improves, but manufacturing time increases
Solution Approach 1:
The dummy gate stack is formed in advance, providing a self-aligned reference structure that guides the fin thinning process. This preliminary action reduces the need for extensive iterative adjustments because the gate spacer and dummy gate stack create a natural alignment reference, thereby reducing manufacturing time while maintaining high precision.
Solution Approach 2:
The feedback process is optimized by measuring fin widths at strategic points and making targeted adjustments rather than continuous iterations. The process measures fin widths, compares with targets, and adjusts etching parameters only when necessary, reducing unnecessary manufacturing time while achieving the required precision through intelligent feedback control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise control over fin widths, enhancing gate control, reducing fin-width variation, and improving current density and threshold voltage control, thereby addressing the scaling challenges in FinFET production.
Implementation Method 1
performing a first thinning process on the first semiconductor fin using the first etching recipe
Data Source
AI summary
A method includes forming isolation regions extending into a semiconductor substrate. A semiconductor strip is between the isolation regions. The method further includes recessing the isolation regions so that a top portion of the semiconductor strip protrudes higher than top surfaces of the isolation regions to form a semiconductor fin, measuring a fin width of the semiconductor fin, generating an etch recipe based on the fin width, and performing a thinning process on the semiconductor fin using the etching recipe.