FinFET Fin Trim Process Delayed for Epitaxial Source Drain Growth
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, the short channel effect (SCE) and current crowding issues in FinFETs become more pronounced, affecting the performance and integration density of electronic components.
Innovation Solution
The fin trim process is delayed until after the source/drain regions are formed, allowing for a greater fin surface area during epitaxial growth and reducing the vertical distance between channel and source/drain regions, which enhances gate control and reduces SCE, thereby improving FinFET performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the fin trim process is performed before source/drain region formation, then the gate control is improved and short channel effect is reduced, but the fin surface area available for epitaxial growth is reduced
Solution Approach 1:
The fin trim process is delayed until after source/drain region formation rather than being performed beforehand. This reversal of the conventional sequence allows the fin to maintain its larger original dimensions during epitaxial growth, providing greater surface area for source/drain formation, while still achieving the desired gate control improvement through trimming at the later stage when dummy gate stacks are removed.
2Area of moving object
If the fin trim process is delayed until after source/drain region formation, then the fin surface area for epitaxial growth is increased, but the vertical distance between channel and source/drain regions increases
Solution Approach 1:
The fin trim process is strategically delayed to the timing when dummy gate stacks are removed and before replacement gate stacks are formed. This timing allows the fin to maintain its full dimensions during source/drain epitaxial growth, maximizing the surface area available for growth, while the subsequent trimming step before final gate formation ensures the vertical distance is optimized for reduced current crowding effects.
3Productivity
If feature size is reduced to improve integration density, then more components can be integrated into a given area, but short channel effect and current crowding issues become more pronounced
Solution Approach 1:
The fin trim process is delayed to a later stage in the manufacturing sequence, allowing smaller feature sizes to be maintained throughout earlier processing steps including source/drain epitaxial growth. This enables higher integration density while the delayed trimming ensures optimal gate control is achieved at the final stage, mitigating short channel effects in the scaled-down devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances gate control, reduces current crowding effects, and improves the performance of FinFETs in applications like direct current and ring oscillator applications by allowing for more efficient epitaxial source/drain formation and reduced defects.
Implementation Method 1
growing an epitaxial source/drain in the fin adjacent the channel region
Data Source
AI summary
In an embodiment, a method includes: forming a fin extending from a substrate, the fin having a first width and a first height after the forming; forming a dummy gate stack over a channel region of the fin; growing an epitaxial source/drain in the fin adjacent the channel region; and after growing the epitaxial source/drain, replacing the dummy gate stack with a metal gate stack, the channel region of the fin having the first width and the first height before the replacing, the channel region of the fin having a second width and a second height after the replacing, the second width being less than the first width, the second height being less than the first height.