FinFET Transistor Fin Width Control via CMP Planarization
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Solution Overview
Problem
Existing FinFET transistor production methods face challenges in achieving narrow fin-like channel regions and sufficient nitride for chemical mechanical polishing (CMP) due to fluctuations in fin width and limited nitride availability, leading to scalability issues and planarization problems.
Innovation Solution
The method involves anisotropic etching using a modified hard mask to the residual height of the etched-back STI oxide filling, creating a gap region that is filled with an insulation layer before gate dielectric and gate formation, and using a polysilicon filling with subsequent planarization and metal silicide deposition to ensure narrow channels and robust production.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If isotropic silicon etch is used to thin the channel region, then the channel region can be thinned, but fluctuations of the width of the fin-like channel regions occur
Solution Approach 1:
The patent replaces the chemical isotropic etching process with a mechanical/physical polishing process (chemical mechanical polishing or CMP). This substitution eliminates the lateral etching that causes fin width fluctuations, as CMP provides planarization without the directional bias and lateral erosion inherent in chemical etching methods.
2Length of moving object
If the active silicon layer is etched through completely to create narrow channels, then narrow fin-like channel regions are achieved, but not enough nitride remains for CMP
Solution Approach 1:
The patent performs preliminary planarization of the STI oxide filling before completely removing the nitride hard mask. By polishing the STI oxide to the appropriate level first, the process ensures that sufficient nitride thickness remains when the hard mask is fully removed, providing adequate CMP stop layer for subsequent processing steps while still achieving the desired narrow channel dimensions.
3Quantity of substance
If STI trenches are widened to provide enough nitride for CMP, then sufficient nitride is available for polishing, but the fin-like channel regions become relatively wide
Solution Approach 1:
The patent performs preliminary planarization of the STI oxide filling before completely removing the nitride hard mask. By polishing the STI oxide to the appropriate level first, the process ensures that sufficient nitride thickness remains when the hard mask is fully removed, providing adequate CMP stop layer for subsequent processing steps while still achieving the desired narrow channel dimensions.
Solution Approach 2:
The patent uses the STI oxide filling as a sacrificial reference structure that defines the final channel width. The oxide is deposited and planarized to the target channel width, then used as a template during subsequent etching steps. This copying approach ensures precise channel width control while maintaining adequate nitride thickness for CMP operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the creation of FinFET transistors with excellent scalability and robust production, achieving very narrow fin-like channel regions while maintaining enough nitride for CMP, thereby improving transistor performance and manufacturing reliability.
Implementation Method 1
The active silicon layer 1 is anisotropically etched using the modified hard mask as mask
Implementation Method 2
enough nitride for the CMP step
Data Source
AI summary
The present invention provides a FinFET transistor arrangement produced using a method with the steps: providing a substrate (106, 108); forming an active region (1) on the substrate a fin-like channel region (113b′; 113b″). Formation of the fin-like channel region (113b′; 113b″) has the following steps: forming a hard mask (S1-S4) on the active region (1); anisotropic etching of the active region (1) using the hard mask (S1-S4) forming STI trenches (G1-G5) having an STI oxide filling (9); polishing-back of the STI oxide filling (9); etching-back of the polished-back STI oxide filling (9); selective removal of components of the hard mask forming a modified hard mask (S1′-S4′); anisotropic etching of the active region (1) using the modified hard mask (S1′-S4′) forming widened STI trenches (G1′-G5′), the fin-like channel regions (113b′; 113b″) of the active region (1) remaining for each individual FinFET transistor.