FinFET Fin Structure With Semiconductor Layer to Constrain Wiggling
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Solution Overview
Problem
The challenge in the semiconductor industry is to form reliable semiconductor devices at increasingly smaller sizes due to the complexity and difficulty of fabrication processes as feature sizes decrease, leading to issues with fin wiggling and yield in FinFET structures.
Innovation Solution
The solution involves forming a semiconductor device structure with FinFETs where a semiconductor layer with a similar lattice constant to the substrate constrains the wiggling of fins, improving yield by using a combination of photolithography and self-aligned processes for patterning, and forming a gate stack wrapped around the fins with a dielectric layer and gate electrode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes are decreased to increase functional density, then production efficiency is improved and costs are lowered, but fabrication process complexity increases and device reliability deteriorates
Solution Approach 1:
The fabrication process is divided into multiple patterning steps (e.g., self-aligned double patterning, self-aligned triple patterning) where each step creates a portion of the final pattern. This segmentation allows precise control of fine features while maintaining reliability through incremental processing rather than attempting to create all features in a single step.
Solution Approach 2:
Sacrificial layers are formed and patterned in advance before the actual fin structures are created. These preliminary sacrificial features guide subsequent spacer formation and material deposition, ensuring precise positioning and reducing variability in the final device structure, thereby maintaining reliability at scaled dimensions.
2Area of stationary object
If feature sizes are decreased to increase functional density, then chip area utilization is improved, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
Spacer layers act as intermediary structures that define the final fin dimensions and positions. The spacers are formed conformally on sacrificial layers and then the sacrificial layers are removed, transferring the spacer pattern to the final structure. This intermediary approach enables precise dimensional control that is difficult to achieve through direct lithography alone at scaled feature sizes.
Solution Approach 2:
The patent employs multiple deposition and etching parameters across different process steps to achieve precise feature dimensions. By controlling film thickness, deposition temperature, etch selectivity, and other parameters in each patterning step, the process maintains manufacturing precision even as overall feature sizes decrease to increase functional density.
3Manufacturing precision
If multi-patterning processes are used to create fins, then patterning precision is improved, but process complexity increases
Solution Approach 1:
The self-aligned patterning process allows each subsequent step to automatically align with previous features without requiring additional alignment steps or complex mask positioning. The spacers self-align to the sacrificial layers, and subsequent materials self-align to the spacer structures, reducing process complexity despite multiple patterning steps.
Solution Approach 2:
The patent transitions from two-dimensional planar patterning to three-dimensional fin structures through vertical spacer formation and conformal deposition. This dimensional transition enables precise lateral patterning control through vertical film thickness control, achieving high patterning precision while managing process complexity through the added dimension.
Data Source
AI summary
A method for forming a semiconductor device structure is provided. The method includes providing a substrate, a fin, and a semiconductor layer. The fin is over the substrate, the semiconductor layer is over the fin, the substrate and the fin are made of different materials, and the fin and the semiconductor layer are made of different materials. The method includes forming a dielectric layer over the semiconductor layer and the fin. The method includes forming a semiconductor structure over a sidewall of the dielectric layer. The method includes removing a first top portion of the dielectric layer over a top surface of the semiconductor layer. The method includes forming a gate over the semiconductor layer, the dielectric layer, and the semiconductor structure.