FinFET Flank Exposure Using Angled Atomic Layer Etching
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Solution Overview
Problem
As semiconductor devices continue to scale down in size, existing manufacturing methods for FinFETs face challenges in achieving precise control over the fin structure, particularly in removing spacer material and oxide layers without damaging the gate spacers or fins.
Innovation Solution
The manufacturing method employs an atomic layer etching (ALE) process with angled ion bombardment to selectively remove spacer material and oxide layers from the sidewalls of the fins, while preserving the gate spacers and maintaining the fin structure integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching methods are used to remove spacer material, then the removal process is simple, but the fin structure and gate spacers are damaged
Solution Approach 1:
The patent changes the parameters of the etching process by using atomic layer etching (ALE) with controlled ion bombardment energy and angle. By adjusting these parameters, the etching process achieves high precision in removing spacer material while preventing damage to the fin structure and gate spacers through self-limiting etch depth control
Solution Approach 2:
The patent replaces conventional mechanical/chemical etching methods with atomic layer etching that uses controlled ion bombardment. This substitution enables precise atomic-level removal of material through physical sputtering combined with chemical reactions, providing better control over etch depth and preventing structural damage
2Manufacturing precision
If aggressive etching is used to expose flank portions, then the flank portions are exposed, but the gate spacers are damaged
Solution Approach 1:
The patent modifies the etching parameters by using low-energy ion bombardment in an atomic layer etching process. This parameter change allows the flank portions to be exposed through precise, controlled material removal while maintaining the integrity of gate spacers by preventing excessive etching
Solution Approach 2:
The patent employs periodic cycles of precursor exposure and purging in the atomic layer etching process. This periodic action allows for controlled, incremental removal of spacer material layer by layer, enabling precise exposure of flank portions without compromising gate spacer integrity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for precise removal of spacer material and oxide layers, ensuring that the flank portions of the fins are exposed without damaging the gate spacers, thereby enhancing the manufacturing yield and device performance.
Implementation Method 1
The manufacturing method employs an atomic layer etching (ALE) process with angled ion bombardment to selectively remove spacer material and oxide layers from the sidewalls of the fins
Data Source
AI summary
A fin-type field effect transistor comprising a substrate, at least one gate stack and epitaxy material portions is described. The substrate has fins and insulators located between the fins, and the fins include channel portions and flank portions beside the channel portions. The at least one gate stack is disposed over the insulators and over the channel portions of the fins. The epitaxy material portions are disposed over the flank portions of the fins and at two opposite sides of the at least one gate stack. The epitaxy material portions disposed on the flank portions of the fins are separate from one another.