FinFET Flared Fin Profile for Drive Current and Area Trade-off
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Solution Overview
Problem
The production of FinFET transistors faces challenges due to their small size, which complicates manufacturing and conflicts with the need for increased drive currents without occupying more chip area, as larger gate widths are required for higher drive currents but clash with the goal of reducing semiconductor device sizes.
Innovation Solution
The method involves forming FinFET devices with a specific fin structure, including upper and lower portions with controlled widths and slopes, using anisotropic plasma etch processes to create a flared profile that minimizes deformation and defects, and depositing dielectric materials between the fins, allowing for increased drive current without expanding chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If gate widths are increased to achieve greater drive currents, then drive current increases, but chip area occupation increases
Solution Approach 1:
The patent transitions from planar transistors to three-dimensional FinFET structures by creating vertical fins extending from the substrate. This dimensional change allows the gate to control current flow in three dimensions, achieving higher drive current without proportionally increasing the horizontal chip area occupation.
Solution Approach 2:
The patent implements a flared fin profile where the lower portion of the fin is wider than the upper portion, creating a nested structure. This allows the gate to effectively control a larger effective channel width while maintaining a compact footprint, as the wider base provides additional current pathways without increasing the top-down chip area.
2Area of stationary object
If FinFET size is reduced to occupy less chip area, then chip area usage improves, but manufacturing complexity and defects increase
Solution Approach 1:
The patent performs preliminary patterning to form the flared fin profile before gate formation. By pre-shaping the fin structure with controlled widths at different heights, subsequent manufacturing steps are simplified, and alignment precision requirements are reduced, thereby decreasing overall manufacturing complexity despite the three-dimensional structure.
3Power
If flared fin profile is created to enhance drive current, then drive current increases, but etch process complexity increases
Solution Approach 1:
The patent divides the fin structure into distinct segments: an upper portion with a first width and a lower portion with a second, wider width. This segmentation allows each portion to be optimized independently for its function while simplifying the etch process control, as the process can be tuned to create each segment with specific characteristics rather than attempting to create a continuously varying profile.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of FinFET devices with enhanced drive currents while maintaining compact sizes, reducing manufacturing complexities and optimizing chip area usage.
Implementation Method 1
using anisotropic plasma etch processes to create a flared profile
Implementation Method 2
depositing dielectric materials between the fins
Data Source
AI summary
A FinFET device may include a first semiconductor fin laterally adjacent a second semiconductor fin. The first semiconductor fin and the second semiconductor fin may have profiles to minimize defects and deformation. The first semiconductor fin comprises an upper portion and a lower portion. The lower portion of the first semiconductor fin may have a flared profile that is wider at the bottom than the upper portion of the first semiconductor fin. The second semiconductor fin comprises an upper portion and a lower portion. The lower portion of the second semiconductor fin may have a flared profile that is wider than the upper portion of the second semiconductor fin, but less than the lower portion of the first semiconductor fin.