FinFET Flash Memory With Extended Floating Gate Overlap
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Solution Overview
Problem
Flash memory devices with floating gates and control gates on the same side of the channel face challenges in scaling the gate dielectric, leading to increased leakage and difficulties in forming structures with different overlap capacitances, which hinders efficient charging and discharging of the floating gate.
Innovation Solution
A finFET-based flash memory structure is developed with a control gate dielectric on one side of the semiconductor fin and an independently formed floating gate dielectric on the opposite side, featuring an extended overlap between the drain and floating gate, achieved through specific semiconductor processing steps including conformal deposition and reactive ion etching to form a gate spacer, enhancing charge trapping efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the gate dielectric is scaled down to enhance MOSFET performance, then device performance is improved, but charge leakage from the floating gate increases
Solution Approach 1:
The patent divides the gate structure into two separate gates: a control gate for performance optimization and a floating gate for charge storage. This segmentation allows the control gate dielectric to be scaled down for improved device performance while the floating gate dielectric maintains optimal thickness for charge retention, thereby resolving the contradiction between performance and leakage.
Solution Approach 2:
The floating gate is extracted from the conventional single-gate structure and positioned on the back side of the channel. This extraction enables independent optimization of the floating gate dielectric thickness for charge storage while allowing the control gate dielectric to be scaled independently for performance enhancement without compromising charge retention.
2Manufacturing precision
If a planar MOSFET structure with back-side floating gate is used, then gate dielectric scaling is enabled, but self-aligned double gate formation becomes difficult
Solution Approach 1:
The patent transitions from a planar single-side gate structure to a three-dimensional back-side floating gate structure. By positioning the floating gate on the opposite side of the channel from the control gate, the patent achieves self-alignment through vertical stacking rather than lateral alignment, enabling both gate dielectric scaling and simplified manufacturing.
3Device complexity
If the floating gate and control gate are on the same side of the channel, then device structure is simplified, but overlap capacitance control is limited
Solution Approach 1:
By segmenting the gate structure into control and floating gates positioned on opposite sides of the channel, the patent enables independent control of overlap capacitance. The floating gate can be designed with extended overlap with the drain region to enhance charge trapping, while the control gate maintains standard dimensions, providing versatility in capacitance control without excessive complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for independent scaling of the control and floating gates, improving charge trapping efficiency and enabling larger overlap capacitance, thus enhancing the performance and reliability of the non-volatile memory device.
Implementation Method 1
The floating gate stores a variable amount of charge which tunnels through the floating gate dielectric
Implementation Method 2
the efficiency of charge trapping by the floating gate that is typically generated in the drain of the MOSFET by a hot, or energetic, charge carriers, i.e., hot electrons
Implementation Method 3
A gate spacer reaching above a gate cap layer and the control gate dielectric thereupon is formed by a conformal deposition of a dielectric layer and a reactive ion etch
Data Source
AI summary
A floating gate is formed on one side of the semiconductor fin on a floating gate dielectric. A control gate dielectric is formed on the opposite side of the semiconductor fin and on the floating gate. A gate conductor is formed on the control gate dielectric across the semiconductor fin. A gate spacer reaching above a gate cap layer and the control gate dielectric thereupon is formed by a conformal deposition of a dielectric layer and a reactive ion etch. The control gate dielectric and the material of the floating gate are removed from exposed portions of the semiconductor fin. The gate spacer is thereafter removed and source and drain regions are formed in the semiconductor fin. The overlap between the drain and the floating gate is extended by the thickness of the gate spacer, resulting in an enhanced efficiency in charge trapping in the floating gate.