FinFET Flash Memory Cell Gate Integration
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Solution Overview
Problem
The integration of flash memory cells with FinFET devices has not been successfully achieved in the past, posing challenges for further device scaling and compatibility with sophisticated mask technologies.
Innovation Solution
A method for manufacturing flash memory cells is developed, where semiconductor fins are formed on a substrate, with insulating layers and gate structures created to integrate sense and control gates, allowing for the formation of non-volatile flash memory cells within the process flow of FinFET devices, utilizing a high-k dielectric material to isolate the semiconductor fin from the sense and control gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional planar transistor architectures are used, then manufacturing process is simpler, but device scaling and current drive capability are limited
Solution Approach 1:
The patent transitions from planar two-dimensional transistor architecture to three-dimensional FinFET architecture by forming vertical fins in the semiconductor substrate. This dimensional change increases the effective channel width and surface area for charge carrier flow, thereby enhancing current drive capability while maintaining controllability through the vertical gate structure that wraps around the fin.
Solution Approach 2:
The patent segments the channel region into multiple vertical fins instead of a single planar channel. Each fin acts as an independent current path, and the combined effect of multiple fins provides enhanced current drive capability. The gate electrode wraps around each fin, providing segmented control over each vertical channel region.
2Reliability
If gate dielectric thickness is reduced to increase effective coupling, then gate control improves, but gate leakage and manufacturing difficulty increase
Solution Approach 1:
The patent achieves enhanced gate-to-channel coupling by transitioning to vertical fin structures where the gate electrode wraps around the fin on multiple sidewalls. This three-dimensional gate configuration provides superior electrostatic control and effective coupling without requiring extreme reduction in gate dielectric thickness, thereby avoiding associated manufacturing difficulties and leakage issues.
Solution Approach 2:
The gate electrode structure is nested around the vertical fin, with the gate dielectric layer surrounding the fin and the gate electrode surrounding the dielectric. This nested configuration maximizes the gate-to-channel interaction surface area and provides effective coupling while maintaining manufacturable thicknesses for the dielectric layer.
3Adaptability or versatility
If flash memory cells are integrated with FinFET devices, then device functionality and storage capability are enhanced, but manufacturing process complexity increases
Solution Approach 1:
The patent merges the formation of FinFET devices and flash memory cells into a single integrated manufacturing process. The same semiconductor fins serve as the basis for both the FinFET transistor channels and the flash memory cell structures. Gate electrodes and dielectric layers are formed in a unified sequence that simultaneously creates both device types, thereby enhancing functionality while controlling manufacturing process complexity.
Solution Approach 2:
The semiconductor fin structure serves multiple functions: it provides the channel region for FinFET transistors and simultaneously forms the basis for the memory cell structure in flash memory devices. The gate electrode system is configured to provide both transistor gate control and flash memory control gate functionality, achieving multi-functionality from a unified structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the integration of flash memory cells with improved performance characteristics within the FinFET device manufacturing process, enhancing current drive capability and allowing for effective threshold voltage control through charge accumulation in the floating gate.
Implementation Method 1
a first high-k dielectric (k>5) formed between the sense gate and the first sidewall of the semiconductor fin, a control gate neighbored to the second sidewall of the semiconductor fin, a floating gate arranged between the control gate and the second sidewall of the semiconductor fin, and a second high-k dielectric (k>5) formed between the floating gate and the control gate
Data Source
AI summary
A method of manufacturing a flash memory cell is provided including forming a plurality of semiconductor fins on a semiconductor substrate, forming floating gates for a sub-set of the plurality of semiconductor fins and forming a first insulating layer between the plurality of semiconductor fins. The first insulating layer is recessed to a height less than the height of the plurality of semiconductor fins and sacrificial gates are formed over the sub-set of the plurality of semiconductor fins. A second insulating layer is formed between the sacrificial gates and, after that, the sacrificial gates are removed. Recesses are formed in the first insulating layer and sense gates and control gates are formed in the recesses for the sub-set of the plurality of semiconductor fins. The first and second insulating layers may be oxide layers.