FinFET Flash Memory Device Compatibility with Logic Processes

Solution Overview

Problem

Current Fin-type flash memory devices are not compatible with FinFET logic devices, and their manufacturing processes are costly.

Innovation Solution

A FinFET flash memory device is designed with a first fin as the memory channel, a second fin as the control gate, and a floating gate across both, integrated on an insulating substrate, using a method that includes patterning semiconductor layers, forming dielectric and floating gates, and creating source/drain regions, which is compatible with FinFET logic devices and reduces manufacturing costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If Fin-type flash memory device structure is used, then flash memory functionality is achieved, but compatibility with FinFET logic devices is lost

Engineering Contradiction:

Improvecompatibility with FinFET logic devicesVSAvoiddevice structure complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent applies universality by designing a flash memory device with a FinFET structure that can be manufactured using the same process as FinFET logic devices. The dual-fin configuration (first fin for memory channel, second fin for control gate) enables the device to function as flash memory while maintaining structural compatibility with standard FinFET logic device manufacturing processes, allowing one structure to serve multiple functions.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent segments the flash memory device into two distinct fins: a first fin serving as the memory channel and a second fin serving as the control gate. This segmentation allows each fin to be optimized for its specific function while maintaining overall compatibility with FinFET logic device manufacturing processes.

Inventive Principle:

Principle #1Segmentation

2Ease of manufacture

If conventional Fin-type flash memory manufacturing process is used, then flash memory device is formed, but manufacturing cost is high

Engineering Contradiction:

Improvemanufacturing costVSAvoiddevice structure precision

Core Design Contradiction:

Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent merges the flash memory device structure with the standard FinFET logic device manufacturing process. By combining the formation of the first fin and second fin into the same manufacturing sequence used for logic devices, the patent eliminates the need for separate, costly manufacturing processes while maintaining precise structural control through established FinFET fabrication techniques.

Inventive Principle:

Principle #5Merging (Combining)

3Adaptability or versatility

If FinFET structure is introduced into flash memory, then compatibility with logic devices is achieved, but device structure complexity increases

Engineering Contradiction:

Improvecompatibility with FinFET logic devicesVSAvoiddevice structure complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent applies universality by designing a flash memory device with a FinFET structure that can be manufactured using the same process as FinFET logic devices. The dual-fin configuration (first fin for memory channel, second fin for control gate) enables the device to function as flash memory while maintaining structural compatibility with standard FinFET logic device manufacturing processes, allowing one structure to serve multiple functions.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS8878280B2Flash memory device and method for manufacturing the same

Publication Date: 2014.11.04 INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD

AI summary

The present invention provides a FinFET flash memory device and the method for manufacturing the same. The flash memory device is on an insulating layer, comprising: a first fin and a second fin, wherein the second fin is a control gate of the device; a gate dielectric layer, at side walls and top of the first fin and the second fin; source/drain regions, inside the first fin at both sides of a floating gate.