FinFET Split-Gate Flash Cell Layout for Selective Floating-Gate Coupling
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Solution Overview
Problem
Conventional split-gate non-volatile flash memory cells face challenges in minimizing capacitive coupling between adjacent floating gates, which can affect memory cell operation, and existing methods to avoid this coupling are not always effective.
Innovation Solution
The configuration of memory cells is modified to enhance capacitive coupling between some adjacent floating gates, using a specific fin arrangement and control gate placement to allow for fine-tuning of programming by utilizing the capacitive coupling as a mechanism for improved programming accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If fins are spaced sufficiently far apart to suppress capacitive coupling between floating gates, then capacitive coupling is reduced, but device density and integration are decreased
Solution Approach 1:
A control gate portion is introduced as an intermediary element positioned between adjacent floating gates on different fins. This control gate portion acts as a shield that blocks the capacitive coupling path between floating gates, allowing fins to be placed closer together without suffering from harmful capacitive interference. The intermediary structure enables higher device density while maintaining electrical isolation between adjacent memory cells.
2Object-affected harmful factors
If control gate extends down between adjacent floating gates to suppress capacitive coupling, then capacitive coupling is reduced, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The control gate is segmented into distinct portions: a first portion that wraps around the floating gate on its fin, and a second portion that extends between adjacent fins to shield floating gates on different fins. This segmentation allows the control gate to perform multiple functions - both as a control electrode for its associated floating gate and as a shielding structure for adjacent cells. The segmented design reduces complexity compared to a fully continuous control gate structure while effectively suppressing capacitive coupling.
3Reliability
If conventional methods are used to minimize capacitive coupling, then memory cell operation is stable, but programming resolution and tuning accuracy are insufficient
Solution Approach 1:
Capacitive coupling between floating gates is not uniformly suppressed but is instead locally utilized. The patent employs different spacing between fins: closer spacing for fin pairs where capacitive coupling is desired for programming resolution, and greater spacing for other adjacent fins where coupling should be minimized. This local differentiation of spacing creates varying capacitive coupling strengths that enable fine-tuning of programming accuracy while maintaining overall operational stability through selective coupling regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for finer resolution and accuracy in programming memory cells, particularly useful in applications like artificial neural networks where precise weight tuning is critical, by leveraging capacitive coupling between floating gates for fine-tuning programming without disturbing the programmed state.
Implementation Method 1
Capacitive coupling between adjacent floating gates 6 on different fins 2a could adversely affect memory cell operation
Implementation Method 2
forming a tunnel insulating layer on portions of the fin, and forming a floating gate on the tunnel insulting layer so that the tunnel insulating layer is between the floating gate and the fin
Data Source
Figure 1A
Figure 1B
Figure 2A
AI summary
Memory cells formed on upwardly extending fins of a semiconductor substrate, each including source and drain regions with a channel region therebetween, a floating gate extending along the channel region and wrapping around the fin, a word line gate extending along the channel region and wrapping around the fin, a control gate over the floating gate, and an erase gate over the source region. The control gates are a continuous conductive strip of material. First and second fins are spaced apart by a first distance. Third and fourth fins are spaced apart by a second distance. The second and third fins are spaced apart by a third distance greater than the first and second distances. The continuous strip includes a portion disposed between the second and third fins, but no portion of the continuous strip is disposed between the first and second fins nor between the third and fourth fins.