FinFET Floating Gate Memory Cell Integration
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Solution Overview
Problem
Conventional memory devices require additional processing steps when embedding flash memory or OTP memory within standard FINFET logic semiconductor processes, complicating customization and reliability.
Innovation Solution
A nonvolatile memory device with a floating gate and multiple semiconductor fins, where programming and erase operations are performed by injecting electrons and holes through specific fins, and read operations utilize the floating gate and fin channels as an access transistor, sharing processing steps with standard logic transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If flash memory or OTP memory is embedded within standard FINFET logic semiconductor processes, then customization and reliability are improved, but additional add-on processing steps are required which complicates manufacturing
Solution Approach 1:
The patent merges flash memory and OTP memory functionality directly into the standard FINFET logic semiconductor process by forming memory cells using the same transistor structures and materials. The floating gate is formed from the same material as the logic transistor gate, and both memory and logic devices share common processing steps including fin formation, gate formation, and doping processes, thereby eliminating the need for separate add-on processing steps while maintaining reliability
Solution Approach 2:
The patent creates a universal memory structure that can function as either flash memory or OTP memory depending on the programming method applied. The same fin-based transistor structure with floating gate serves multiple purposes: it can be programmed through hot electron injection for flash memory operation or through direct hole injection for OTP operation, providing multi-functionality without requiring different device structures
2Adaptability or versatility
If multiple semiconductor fins are used for programming and reading operations, then multi-time programmability is achieved, but device structure complexity increases
Solution Approach 1:
The patent segments the memory cell into distinct functional fins: a first-type fin for programming operations (electron injection) and a second-type fin for read operations (access transistor). This segmentation allows independent optimization of each function while maintaining a relatively simple overall structure that avoids the need for multiple specialized fins for each programming cycle
3Adaptability or versatility
If electrons and holes are injected through fins into the floating gate for programming and erase operations, then repeated electrical erasure and re-programming are enabled, but manufacturing precision requirements increase
Solution Approach 1:
The patent achieves repeated programmability by changing the electrical parameters (voltage, current, polarity) applied to the fins rather than changing the physical structure. The same fin structure can be programmed or erased repeatedly by applying different voltage polarities for electron injection or hole injection, avoiding the need for high manufacturing precision variations while enabling multi-time programmability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables repeated electrical erasure and re-programming, providing durable and reliable multi-time programmable and one-time programmable memory solutions with improved read accuracy and minimal impact on existing manufacturing processes.
Implementation Method 1
programming and erase operations of the NVM cell are performed by injecting electrons and holes, respectively, through the third-type fin into the floating gate
Implementation Method 2
programming and erase operations of the NVM cell are performed by injecting electrons and holes, respectively, through the third-type fin into the floating gate
Implementation Method 3
The first-type semiconductor fin and the floating gate form a coupling capacitor of the memory cell
Data Source
AI summary
A nonvolatile memory device may operate with a logic transistor, which includes a transistor gate formed of a material. The memory device includes a floating gate formed of the material, a first-type fin, and a second-type fin. The first-type fin includes a first-type channel, a first-type source, and a first-type drain. The first-type channel, the first-type source, and the first-type drain have a first conductivity type. The second-type fin includes a second-type channel, a second-type source, and a second-type drain. The second-type source and the second-type drain have the first conductivity type. The second-type channel has a second conductivity type opposite to the first conductivity type. The floating gate is positioned on the first-type channel and the second-type channel.