FinFET Isolation Structures Using Flowable CVD and Two-Stage Etching
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Solution Overview
Problem
Conventional deposition methods struggle with forming isolation structures in high aspect ratio trenches, leading to reduced fin height and increased device capacitance, which affects the performance and manufacturing efficiency of semiconductor devices, especially at advanced process technology nodes below the 20 nm node.
Innovation Solution
The use of a flowable Chemical Vapor Deposition (CVD) process with silicon-containing and nitrogen-containing precursors, followed by an anneal process to form flowable dielectric films that can fill narrow gaps and trenches, combined with a two-stage etching process to reduce the dishing effect and enhance planarity of isolation structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional deposition methods are used to form isolation structures in high aspect ratio trenches, then the manufacturing process is simpler, but the fin height is reduced and device capacitance increases
Solution Approach 1:
The patent changes the physical and chemical parameters of the deposition process by using flowable CVD dielectric films with specific flowability characteristics, allowing the material to naturally flow and fill high aspect ratio trenches uniformly, thereby achieving complete trench filling without compromising fin height
Solution Approach 2:
The patent employs composite material strategies by combining flowable CVD dielectric films with specific compositional characteristics that provide both flowability for trench filling and appropriate dielectric properties for isolation functionality, resolving the contradiction between filling capability and electrical performance
2Reliability
If conventional deposition methods are used for isolation structures, then the process is easier to implement, but device capacitance increases affecting performance
Solution Approach 1:
The patent modifies the deposition parameters by implementing a two-stage etching process with optimized timing and chemistry, followed by flowable CVD deposition, which changes the physical state and flow characteristics of the dielectric material to achieve complete trench filling that reduces device capacitance and improves performance
Solution Approach 2:
The patent performs preliminary actions by conducting a two-stage etching process before deposition to create optimized trench profiles with reduced dishing effects, ensuring that subsequent flowable dielectric film deposition can uniformly fill the trenches and achieve the desired electrical characteristics
3Manufacturing precision
If conventional etching processes are used, then the process is simpler, but dishing effect increases reducing isolation structure planarity
Solution Approach 1:
The patent segments the etching process into two distinct stages: a first etching process that removes excess isolation material, and a second etching process that further refines the profile. This segmentation allows each stage to be optimized for specific objectives, reducing dishing effects and improving overall planarity
Solution Approach 2:
The first etching process serves as a preliminary action that prepares the isolation structures by removing excess material and establishing a foundation for the second etching process, which then achieves the final planarity requirements with reduced dishing effects
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively increases the fin height, reduces device capacitance, and improves wafer acceptance test results by minimizing the dishing effect, thereby enhancing semiconductor device performance and manufacturing efficiency.
Implementation Method 1
The use of a flowable Chemical Vapor Deposition (CVD) process with silicon-containing and nitrogen-containing precursors, followed by an anneal process to form flowable dielectric films
Implementation Method 2
followed by an anneal process to form flowable dielectric films that can fill narrow gaps and trenches
Implementation Method 3
combined with a two-stage etching process to reduce the dishing effect and enhance planarity of isolation structures
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming a semiconductor strip protruding above a substrate, forming isolation regions on opposing sides of the semiconductor strip, recessing the isolation regions in a first chamber using a first etching process, and increasing a planarity of the isolation regions in the first chamber using a second etching process.