FinFET Dielectric Isolation via Flowable Oxide and Stressor

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Solution Overview

Problem

Bulk finFETs face challenges with leakage currents and device variability due to lack of effective isolation, leading to degraded electrical performance and increased manufacturing costs compared to silicon-on-insulator (SOI) finFETs.

Innovation Solution

A method involving a sacrificial layer and stressor regions is used to form a semiconductor structure with an insulator region replacing the sacrificial layer, enhancing carrier mobility and isolation without introducing dopants, comprising a bulk semiconductor substrate, a top silicon region, and a stressor region with a specific germanium content.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If bulk finFET structure is used to reduce manufacturing cost, then manufacturing cost is reduced, but leakage currents and device variability increase

Engineering Contradiction:
Improvemanufacturing costVSAvoidleakage current and device variability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The substrate is segmented into isolated regions using insulator regions formed between adjacent fins, creating electrically isolated islands that prevent leakage currents while maintaining the bulk substrate structure for cost-effectiveness

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

An insulator region acts as an intermediary material between the semiconductor substrate and the top silicon region, providing electrical isolation to eliminate leakage paths while allowing the bulk finFET structure to be maintained

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If insulator region is added to reduce leakage currents, then leakage currents are reduced, but device complexity increases

Engineering Contradiction:
Improveleakage current reductionVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The insulator region formation is merged with the existing finFET fabrication process steps, including using the same sacrificial layer removal process and combining stressor region formation with the isolation structure creation, thereby reducing overall process complexity

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If stressor region with germanium content is introduced to improve carrier mobility, then carrier mobility is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improvecarrier mobilityVSAvoidgermanium content control
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The germanium content in the stressor region is optimized to a specific range (40-50%) to achieve the desired stress effect and carrier mobility improvement while maintaining manufacturability and avoiding excessive precision requirements

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach improves carrier mobility and reduces device variability, achieving better electrical performance and lower manufacturing costs by providing effective isolation and stressor regions below the top level of the bulk substrate.

Implementation Method 1

a stressor region disposed adjacent to the metal gate and recessed below a top level of the semiconductor substrate

Methodology Applied
Scientific EffectStress-induced mobility enhancement: Stress Relaxation

Data Source

PatentUS9034715B2Method and structure for dielectric isolation in a fin field effect transistor
Publication Date: 2015.05.19 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US9034715B2 patent drawing
  • US9034715B2 patent drawing
  • US9034715B2 patent drawing

AI summary

A finFET and method of fabrication are disclosed. A sacrificial layer is formed on a bulk semiconductor substrate. A top semiconductor layer (such as silicon) is disposed on the sacrificial layer. The bulk semiconductor substrate is recessed in the area adjacent to the transistor gate and a stressor layer is formed in the recessed area. The sacrificial layer is selectively removed and replaced with an insulator, such as a flowable oxide. The insulator provides isolation between the transistor channel and the bulk substrate without the use of dopants.