FinFET Fuse Integration for Reduced Programming Time
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Solution Overview
Problem
Existing electrically programmable fuse (Efuse) structures in semiconductor devices have limitations in programming time and efficiency, which affect the yield and performance of integrated circuits (ICs).
Innovation Solution
The semiconductor device incorporates a FinFET device with a Fuse device, where the Fuse device has a positive and negative terminal, and a dielectric layer is formed between the FinFET and Fuse devices, leveraging the self-heating effect of the FinFET to enhance thermal migration and reduce programming time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional Efuse structures are used in ICs, then compatibility with CMOS structures is maintained and flexibility is high, but programming time is long and programming efficiency is low
Solution Approach 1:
The patent merges the FinFET device with the Fuse device by forming the Fuse device directly above the FinFET device, sharing common structures such as the substrate, fins, and gate structure. This integration allows the FinFET's self-heating effect to directly accelerate the fusing process, reducing programming time while maintaining efficient programming operations
Solution Approach 2:
The patent changes the physical state and operational parameters by utilizing the FinFET's self-heating effect to increase local temperature at the Fuse device. This temperature increase accelerates the thermal migration process, enabling faster fusing without compromising the overall programming efficiency or CMOS compatibility
2Productivity
If the Fuse device is formed above the FinFET device with a dielectric layer, then thermal migration is enhanced and programming time is reduced, but device complexity increases
Solution Approach 1:
The patent segments the Fuse device into distinct components (first metal layer, second metal layer, conductive plug) formed at different stages, allowing each component to be optimized independently while maintaining overall structural integration with the FinFET device
Solution Approach 2:
The gate structure serves multiple functions: it controls the FinFET device operation and simultaneously provides self-heating to accelerate the Fusing process. The dielectric layer serves as both an electrical isolation layer and a thermal management component, enabling the Fuse device to benefit from FinFET heating while maintaining electrical independence
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces the programming time and enhances the electrical properties of the semiconductor device by utilizing the heat generated by the FinFET for faster and more efficient fusing of the Fuse device.
Implementation Method 1
leveraging the self-heating effect of the FinFET to enhance thermal migration and reduce programming time
Implementation Method 2
a dielectric layer is formed between the FinFET and Fuse devices, leveraging the self-heating effect of the FinFET to enhance thermal migration
Data Source
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AI summary
Semiconductor devices and fabrication methods thereof are provided. An exemplary semiconductor device includes at least one FinFET device. The FinFET device includes a substrate, a plurality of fins protruding from the substrate, at least one gate structure on the substrate and across the plurality of fins by covering portions of side and top surfaces of the plurality of fins, and source/drain regions formed in the plurality of fins at two sides of the gate structure. The semiconductor device also includes a Fuse device formed above the FinFET device. The Fuse device includes a positive terminal and a negative terminal. The negative terminal is electrically connected to at least one source region of the FinFET device and the positive terminal is electrically connected to an external pad. Further, the semiconductor device also includes a dielectric layer formed between the FinFET device and the Fuse device.