Gate Dielectric Dipole Layers for FinFET and GAA Threshold Tuning
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Solution Overview
Problem
Existing CMOS devices, particularly multi-gate devices like FinFET and GAA devices, face challenges in tuning threshold voltages (Vt) due to limited space, making it difficult to achieve both high performance and low power consumption simultaneously.
Innovation Solution
Incorporating p-type and n-type dipole materials into the gate dielectric layers of NMOSFET and PMOSFET transistors, respectively, to tune their threshold voltages without the need for patterning work function metals, suitable for nano-sized transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-gate devices are scaled down to nano-sized dimensions, then device density and integration are improved, but the ability to tune threshold voltages using different work function metals is reduced due to limited space
Solution Approach 1:
The patent changes the parameter used for threshold voltage tuning from work function metal selection to dipole material incorporation. By introducing dipole layers with specific dipole moments into the gate dielectric, the threshold voltage can be adjusted without changing the work function metal, thus resolving the space constraint issue in nano-sized multi-gate devices
Solution Approach 2:
The patent introduces dipole materials as an intermediary between the gate electrode and the channel. These dipole layers act as a mediator that modifies the electric field and potential distribution, enabling threshold voltage tuning without direct modification of the work function metal, thereby preserving device density while achieving voltage control
2Adaptability or versatility
If different work function metals are used to tune threshold voltages, then performance and power consumption are optimized, but device complexity and manufacturing process complexity increase
Solution Approach 1:
The patent makes the gate dielectric structure universal by incorporating dipole materials that can tune threshold voltages for different transistor types (NMOS and PMOS) using the same basic structure. This eliminates the need for different work function metals and their associated complex patterning processes, reducing manufacturing complexity while maintaining threshold voltage control capability
Solution Approach 2:
The patent extracts the threshold voltage tuning function from the work function metal selection process and relocates it to the gate dielectric structure through dipole material incorporation. This separation allows the work function metal to be standardized while the dipole layer provides the tuning capability, thereby reducing device and process complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables flexible adjustment of threshold voltages in both NMOSFETs and PMOSFETs, enhancing performance and reducing power consumption, suitable for advanced IC manufacturing processes.
Implementation Method 1
performing a thermal process to drive at least some dipole elements from the second dipole layer into the high-k dielectric layer
Data Source
AI summary
A method includes providing a first channel layer of a first transistor and a second channel layer of a second transistor over a substrate, forming a dipole layer over the first channel layer and the second channel layer, forming a patterned hard mask covering the second channel layer and exposing the first channel layer, removing the dipole layer from the first channel layer, removing the patterned hard mask, performing a thermal drive-in process, forming an interfacial dielectric layer on the first channel layer and the dipole layer, and forming a high-k dielectric layer on the interfacial dielectric layer. The dipole layer includes a p-dipole material.