FinFET Gain Cell Single-Layer Interconnect Leakage Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The integration of high-density, low-latency memory near computational units in nanoscale transistors is hindered by the high leakage power and reduced data retention time in traditional SRAM and GC-eDRAM technologies, especially at advanced process nodes, due to increased leakage currents and parasitic capacitance drops.
Innovation Solution
A FinFET gain cell design is implemented, featuring a write port with at least one FinFET transistor and a read port with another FinFET transistor, connected by a single layer interconnect with different heights at the diffusion and gate connections, which reduces leakage and enhances data retention time without requiring additional process steps or complex interconnections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional SRAM is used for embedded memory, then high-speed operation is achieved, but leakage power increases and density decreases
Solution Approach 1:
The patent changes the fundamental operating parameters of the memory cell by using gain-cell eDRAM architecture with FinFET transistors, altering the storage mechanism from static latch (SRAM) to dynamic capacitor-based storage with regenerative gain cells, thereby reducing leakage power while maintaining acceptable speed through periodic refresh operations
Solution Approach 2:
The patent replaces the mechanical/electrical latch mechanism of SRAM with a capacitor-based electrical storage mechanism in eDRAM, where data is stored as voltage on capacitors and refreshed periodically, eliminating the continuous static power consumption of SRAM latch structures
2Loss of energy
If GC-eDRAM is used to reduce leakage power, then density increases and leakage decreases, but data retention time deteriorates at advanced process nodes
Solution Approach 1:
The patent changes the transistor architecture from planar to FinFET, which fundamentally alters the electrical characteristics including leakage current profiles and capacitance values, enabling better data retention at advanced process nodes through improved gate control and reduced short-channel effects
Solution Approach 2:
The patent uses standard digital logic FinFET transistor designs and manufacturing processes to create the memory cell, copying proven transistor structures and optimizing them for memory application, thereby achieving reliable data retention without requiring specialized process steps
3Ease of manufacture
If FinFET manufacturing constraints are applied, then manufacturing simplicity is maintained, but interconnect complexity increases due to height differences at diffusion and gate connections
Solution Approach 1:
The patent addresses the interconnect height difference issue by utilizing the vertical dimension - routing the interconnect through different layers or at different heights in the three-dimensional FinFET structure, thereby connecting diffusion and gate nodes without adding horizontal complexity or requiring additional process steps
Data Source
AI summary
A FinFET gain cell includes a write port, read port and storage node. The write port includes at least one write FinFET transistor and has write word-line (WWL) and write bit-line (WBL) inputs. The read port includes at least one FinFET read transistor and has a read word-line (RWL) input and a read bit-line (RBL) output. The storage node stores a data level written from said WBL. The storage nodes includes a single layer interconnect which connects the write port output diffusion connection to the read port input gate connection. The height of the single layer interconnect at the write port output diffusion connection is different from the height of the single layer interconnect at the read port input gate connection.