FinFET Trench Gap Fill With Periodic Nitride Layers to Prevent Voids

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Solution Overview

Problem

Current semiconductor manufacturing techniques face challenges in reducing air gaps and voiding during the gap fill process, particularly in FinFET structures, leading to increased contact resistance and device yield loss due to delamination and trench-to-trench variations.

Innovation Solution

The method involves depositing a liner layer on a substrate and alternatingly exposing it to titanium and nitrogen-containing reactants to form titanium silicon nitride, followed by exposing it to molybdenum precursors to create a bulk molybdenum film, with regular intervals of titanium nitride deposition within the molybdenum fill to prevent void formation and enhance gap fill performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional gap fill processes are used to deposit metal in FinFET structures, then the manufacturing process is simple, but air gaps and voids form leading to increased contact resistance and device yield loss

Engineering Contradiction:
Improvedevice yieldVSAvoidgap fill uniformity
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The gap fill process is segmented into multiple alternating deposition cycles of liner material and metal gap fill material, rather than depositing metal in a single continuous step. This segmentation allows better control over void formation and improves gap fill uniformity while maintaining manufacturing simplicity

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs periodic alternating deposition cycles where liner material is deposited followed by metal gap fill material deposition, repeated multiple times. This periodic action prevents continuous metal deposition that causes voiding, thereby improving reliability and reducing air gaps in FinFET structures

Inventive Principle:
Principle #19Periodic action

2Speed

If larger gate width is used to increase drive current and speed, then transistor performance improves, but transistor size increases

Engineering Contradiction:
Improvetransistor speedVSAvoidtransistor size
Core Design Contradiction:
SpeedVSLength of moving object

Solution Approach 1:

The patent utilizes the vertical dimension by forming three-dimensional FinFET structures with fins extending upward from the substrate. This allows the gate to wrap around the fin channel, providing greater gate control and effective width without increasing the planar footprint, thus improving speed while minimizing transistor size

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Quantity of substance

If feature sizes are reduced to achieve greater circuit density, then circuit density increases, but contact resistance increases due to air gap formation

Engineering Contradiction:
Improvecircuit densityVSAvoidcontact resistance
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent deposits a liner material layer before depositing the metal gap fill material. This preliminary liner layer action prevents void formation and ensures complete gap filling at reduced feature sizes, thereby maintaining low contact resistance while achieving high circuit density

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses a composite structure consisting of alternating liner material and metal gap fill material layers. This composite approach ensures proper gap filling and reduces air gaps in miniaturized FinFET structures, maintaining reliable electrical contact while achieving high circuit density

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces voiding and maintains a high metal percentage within the trench, resulting in lower resistance and improved electrical contact, thereby enhancing the reliability and performance of semiconductor devices.

Implementation Method 1

depositing a liner layer on a substrate

Methodology Applied
Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Implementation Method 2

depositing a liner layer on a substrate

Methodology Applied
Scientific EffectChemical Vapour Deposition: Chemical Vapour Deposition

Implementation Method 3

depositing a metal gap fill material on the liner layer

Methodology Applied
Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Implementation Method 4

depositing a metal gap fill material on the liner layer

Methodology Applied
Scientific EffectChemical Vapour Deposition: Chemical Vapour Deposition

Implementation Method 5

depositing a metal material on the metal gap fill material

Methodology Applied
Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Implementation Method 6

depositing a metal material on the metal gap fill material

Methodology Applied
Scientific EffectChemical Vapour Deposition: Chemical Vapour Deposition

Data Source

PatentUS20240420998A1Reduction of Air Gaps in FinFET Structures
Publication Date: 2024.12.19 APPLIED MATERIALS INC
  • US20240420998A1 patent drawing
  • US20240420998A1 patent drawing
  • US20240420998A1 patent drawing

AI summary

Methods of forming transistors, e.g., FinFETs, are described. A conformal liner layer is formed in a trench. A metal nitride material is introduced in regular or semi-regular intervals during a metal gap fill of a trench structure to prevent the formation of voids (air gaps) within the structure. The metal nitride material and the metal gap fill material may be deposited by atomic layer deposition methods.