FinFET Gap Structure Reduces Parasitic Capacitance

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

FinFET devices with multiple fins experience reduced alternating current performance due to parasitic capacitance, limiting their drive strength and increasing transistor delay time.

Innovation Solution

A semiconductor device with a defined gap, such as an air or vacuum gap, is created between the gate and the source/drain regions by forming a first spacer structure, a sacrificial spacer, and a second spacer structure, and removing the sacrificial spacer to reduce parasitic capacitance and enhance AC performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If multiple fins are used in FinFET device, then drive strength is increased, but parasitic capacitance increases which restricts AC performance

Engineering Contradiction:

Improvedrive strengthVSAvoidparasitic capacitance

Core Design Contradiction:

PowerVSObject-generated harmful factors

Solution Approach 1:

The patent extracts the harmful parasitic capacitance by removing the dummy gate structure between source and drain regions, creating a gap that eliminates the capacitive coupling path while preserving the beneficial multiple fin structure for drive strength

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The device is segmented into discrete regions with the gap physically separating source and drain regions, allowing independent optimization of each region while maintaining overall device performance

Inventive Principle:

Principle #1Segmentation

2Power

If multiple fins are used in FinFET device, then drive strength is increased, but transistor delay time increases

Engineering Contradiction:

Improvedrive strengthVSAvoidtransistor delay time

Core Design Contradiction:

PowerVSLoss of time

Solution Approach 1:

By extracting/removing the dummy gate that causes parasitic capacitance, the patent reduces the time constant associated with charging/discharging parasitic capacitances, thereby reducing transistor delay time while maintaining multiple fins for drive strength

Inventive Principle:

Principle #2Taking out (Extraction)

3Object-generated harmful factors

If dummy gate is removed to create gap, then parasitic capacitance is reduced, but manufacturing complexity increases

Engineering Contradiction:

Improveparasitic capacitanceVSAvoidmanufacturing process complexity

Core Design Contradiction:

Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The dummy gate is removed at an early stage in the fabrication process before subsequent processing steps, simplifying later manufacturing steps while achieving the desired gap structure for reduced parasitic capacitance

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

Spacer structures are used as intermediary elements to define the gap dimensions and provide structural support during fabrication, making the complex gap formation process more controllable and manufacturable

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS9871121B2Semiconductor device having a gap defined therein

Publication Date: 2018.01.16 QUALCOMM INC

AI summary

In a particular embodiment, a method includes forming a first spacer structure on a dummy gate of a semiconductor device and forming a sacrificial spacer on the first spacer structure. The method also includes etching a structure of the semiconductor device to create an opening, removing the sacrificial spacer via the opening, and depositing a material to close to define a gap.