FinFET Gate Air Gaps to Prevent Line-End Bridging
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Solution Overview
Problem
Conventional FinFET device fabrication methods face challenges such as small process windows in the gate-replacement process, leading to leakage and line-end bridging issues due to incomplete removal of dummy gates, which affects device performance and yield.
Innovation Solution
A 'pull back' process is performed during the gate replacement process to widen the opening and create air gaps between adjacent gate structures, reducing the risk of line-end bridging and improving electrical isolation by using lateral etching to remove remnants of the dummy gate layer and forming air gaps in the dielectric material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional gate replacement process is used, then device fabrication can proceed, but small process windows lead to leakage and line-end bridging defects
Solution Approach 1:
The patent performs a 'pull back' etching step before the final gate formation to pre-widen the opening and remove dummy gate remnants. This preliminary action creates a larger process window for subsequent steps, preventing line-end bridging and leakage defects that would otherwise occur due to tight tolerances in conventional processes.
Solution Approach 2:
The gate replacement process is divided into multiple sequential steps: opening formation, pull back etching to widen the opening and remove remnants, air gap formation, and final gate deposition. This segmentation allows each step to be optimized independently, with the pull back step specifically addressing the process window limitation by creating additional margin.
2Ease of manufacture
If dummy gates are not completely removed, then fabrication can continue, but line-end bridging occurs between adjacent gate structures
Solution Approach 1:
The pull back etching step is performed as a preliminary action before final gate formation to completely remove dummy gate remnants and widen the opening. This prevents line-end bridging from occurring while maintaining fabrication continuity, as the process is designed to ensure complete removal without compromising subsequent steps.
Solution Approach 2:
The patent converts the potential harm of aggressive etching (which could damage surrounding structures) into a benefit by using the pull back step to widen the opening and remove remnants. The same etching process that removes dummy gates also creates air gaps and enlarges the process window, turning a potentially harmful action into a beneficial one.
3Reliability
If opening size is increased to prevent bridging, then electrical isolation improves, but device area increases
Solution Approach 1:
The patent applies local quality by forming air gaps specifically in the regions between adjacent gate structures where electrical isolation is needed, rather than uniformly increasing the opening size across the entire device. This localized approach improves electrical isolation at critical interfaces while minimizing the overall device area increase.
Solution Approach 2:
The patent introduces air gaps (effectively porous structure) between adjacent gate structures to improve electrical isolation. The air gaps provide excellent electrical insulation with minimal space requirement, as air has extremely low conductivity. This allows improved isolation without proportionally increasing the device area, unlike solid dielectric materials that would require more volume.
Data Source
AI summary
A semiconductor device includes a first gate structure disposed over a substrate. The first gate structure extends in a first direction. A second gate structure is disposed over the substrate. The second gate structure extends in the first direction. A dielectric material is disposed between the first gate structure and the second gate structure. An air gap is disposed within the dielectric material.