Multi-Gate FinFET Gate Alignment via Epitaxial Protective Layers
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Solution Overview
Problem
The existing methods for producing FinFETs face challenges in aligning the gate electrode with the central location of the fin, leading to imbalanced series resistance between the drain and source electrodes, causing instability in the drain-electrode current and affecting the component performance.
Innovation Solution
The method involves forming a channel and gate medium layers on a substrate, followed by an amorphous silicon layer etching to create fins, and using an epitaxial growth process to form protective layers that allow precise alignment of the gate electrode with the fin, ensuring balanced series resistance through selective etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a pattern composition process such as photoetching is used to form the gate electrode, then the gate electrode can be formed on the substrate, but the gate electrode cannot be accurately aligned with the central location of the fin due to limited pattern composition process precision
Solution Approach 1:
The method performs preliminary actions by forming protective layers and grooves before forming the gate electrode. Specifically, protective layers are grown on both sides of the fin structure, and grooves are etched to expose the substrate at the central location. This preliminary structuring enables precise gate electrode alignment without relying on limited pattern composition process precision, as the groove physically guides the gate electrode placement at the fin center.
2Reliability
If the gate electrode is not accurately aligned with the central location of the fin, then the production process is simpler, but the series resistance between drain and source electrodes becomes imbalanced
Solution Approach 1:
The method employs self-service by using the fin structure itself and epitaxially grown protective layers as alignment references. The protective layers are grown symmetrically from both sides toward the middle, and the groove etching process automatically centers itself on the fin structure. This self-aligning mechanism ensures the gate electrode is precisely positioned at the fin center without requiring external alignment tools or complex patterning, thereby ensuring balanced series resistance and stable drain-electrode current.
3Manufacturing precision
If epitaxial growth process is used to form protective layers, then the gate electrode can be precisely aligned with the fin, but the production time increases
Solution Approach 1:
The method merges multiple functions into the epitaxial growth process. The same epitaxial growth step that forms the protective layers also simultaneously creates the structural framework for alignment and defines the groove locations. By combining protective layer formation, alignment reference creation, and groove positioning into a single integrated process step, the method achieves high precision alignment while minimizing the total production time compared to using separate steps for each function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach stabilizes the drain-electrode current and enhances the component performance of the multi-gate FinFET by accurately aligning the gate electrode, reducing series resistance imbalance and improving overall device stability.
Implementation Method 1
forming, by using an epitaxial growth process, a first protective layer from both sides to the middle of the substrate along a length direction of the at least one fin until a groove is formed in a middle location along the length direction of the at least one fin
Implementation Method 2
etching the amorphous silicon layer by using an etching process, to form at least one fin
Data Source
AI summary
A method for producing a multi-gate fin field-effect transistor (FinFET) is provided. The method includes forming a channel layer and a gate medium layer on a substrate; forming an amorphous silicon layer on the substrate, and etching the amorphous silicon layer, to form at least one fin; forming, by using an epitaxial growth process, a first protective layer from both sides to the middle of the substrate along a length direction of the at least one fin until a groove is formed in a middle location along the length direction of the at least one fin; forming a gate electrode layer on the substrate, performing planarization processing on the gate electrode layer to expose the first protective layer, and etching away the first protective layer by using an etching process, so as to form a gate electrode; and forming a source electrode and a drain electrode on the substrate.