FinFET Gate-All-Around Structure for Electrostatic Control
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Solution Overview
Problem
Current FinFET technologies face challenges in achieving ultimate gate-length scaling and electrostatics, with gate-all-around FETs presenting complex fabrication processes and difficulties in implementing multiple gate-oxide thicknesses, while inserted-oxide FinFETs require improvements in drive current, parasitic capacitance, and short channel control.
Innovation Solution
A semiconductor structure is developed with a layered fin overlying a substrate, featuring alternating semiconductor and insulator layers, where high-K dielectric material is surrounded by low-K dielectric material, enhancing gate coupling and reducing parasitic capacitance through a metal gate and dielectric spacer configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate-all-around FET structure is used to achieve superior electrostatics, then electrostatic control is improved, but fabrication complexity increases due to forming spacers and filling gate metal between nanowires
Solution Approach 1:
The fin structure is segmented into multiple semiconductor layers separated by sacrificial layers, allowing the gate to wrap around each segment individually. This segmentation enables superior electrostatic control through gate-all-around configuration while simplifying fabrication by processing each segment separately rather than attempting to form a continuous gate around a solid fin.
Solution Approach 2:
Sacrificial layers are extracted from the fin structure during fabrication, creating gaps that allow gate material to access and surround the semiconductor layers. The sacrificial layers are temporarily introduced and then removed, enabling the gate to be formed in positions that would be inaccessible in a conventional fin structure, thereby achieving gate-all-around electrostatics with simplified processing.
2Ease of manufacture
If conventional FinFET structure is used, then fabrication is simpler, but drive current and short channel control are insufficient
Solution Approach 1:
The gate structure transitions from planar (conventional FinFET) to three-dimensional gate-all-around configuration by utilizing the vertical dimension created by removing sacrificial layers. This dimensional change allows the gate to contact the channel from top, bottom, and sidewalls, dramatically improving electrostatic control and drive current while maintaining fabrication simplicity through the sacrificial layer approach.
Solution Approach 2:
The fin structure employs composite materials with alternating semiconductor layers and sacrificial layers, allowing different materials to serve different functions. The semiconductor layers provide channel transport while the sacrificial layers enable gate access, creating a composite structure that achieves superior electrical performance without proportionally increasing fabrication complexity.
3Device complexity
If inserted-oxide FinFET is used to achieve trade-off between process challenges and electrostatics, then process complexity is reduced, but drive current and parasitic capacitance need improvement
Solution Approach 1:
The dielectric material is varied locally within the fin structure, with high-K dielectric placed in specific regions where electrostatic control is most needed (at the gate-semiconductor interface) and low-K dielectric placed in regions where parasitic capacitance reduction is prioritized. This local differentiation of dielectric properties optimizes both drive current and parasitic capacitance while maintaining process simplicity.
Solution Approach 2:
The dielectric constant parameter is changed by using different dielectric materials in different locations. High-K dielectric is used to enhance gate coupling and drive current, while low-K dielectric is used to reduce parasitic capacitance. By changing this material parameter strategically throughout the structure, the device achieves improved electrical performance without increasing process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves drive current, reduces parasitic capacitance, and enhances short channel control by optimizing gate coupling and source/drain-to-channel coupling, addressing the limitations of conventional FinFETs.
Implementation Method 1
The insulator includes a high-K dielectric material surrounded by a low-K dielectric material, which are in contact with the two adjacent semiconductor layers
Implementation Method 2
reduces parasitic capacitance through a metal gate and dielectric spacer configuration
Data Source
AI summary
A method of manufacturing an integrated circuit is provided. According to the method, a layered fin including a plurality of sacrificial layers and semiconductor layers wherein two adjacent semiconductor layers are separated by the sacrificial layer is provided on a semiconductor substrate. A gate over the layered fin and a spacer surrounding a sidewall of the gate are then formed. The sacrificial layers are subsequently removed to provide a structure in which two adjacent semiconductor layers are separated by a gap. The method further includes forming an insulator in the gap and forming source and drain regions located on the layered fin. The insulator includes a high-K dielectric material surrounded by a low-K dielectric material, both of which are in contact with the two adjacent semiconductor layers.