FinFET Gate Cross-Sectional Area Variation for Threshold Voltage Control
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Solution Overview
Problem
FinFET transistors face challenges in achieving adjustable threshold voltage and optimizing spatial improvements due to competing physical constraints, limiting the ability to fully realize high-yield and high-performance integrated circuit designs.
Innovation Solution
The method involves forming semiconductor fins with distinct cross-sectional areas for the gate and terminal regions, allowing for the adjustment of threshold voltage by varying the cross-sectional area of the gate region relative to the terminal region through sacrificial gate removal and subsequent etching or epitaxial growth, thereby modifying the contact area between the fin and the gate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the semiconductor fin cross-sectional area is reduced to improve spatial utilization and transistor density, then the transistor size decreases and spatial improvements are realized, but the threshold voltage control becomes limited and performance optimization is constrained
Solution Approach 1:
The patent applies local quality by creating a non-uniform cross-sectional area distribution along the semiconductor fin length. The gate area portion has a different cross-sectional area than the terminal area portion, allowing local optimization of electrical characteristics without reducing overall transistor size. This enables independent control of threshold voltage through the gate area dimensions while maintaining adequate contact area at the terminal for current flow.
Solution Approach 2:
The semiconductor fin is segmented into distinct functional regions: a gate area portion and a terminal area portion. This segmentation allows each region to be optimized independently - the gate area for threshold voltage control and the terminal area for current conduction - thereby resolving the contradiction between size reduction and performance optimization.
2Adaptability or versatility
If the semiconductor fin cross-sectional area is increased to improve threshold voltage control and electrical performance, then the threshold voltage becomes more controllable and performance is enhanced, but the transistor size increases and spatial utilization deteriorates
Solution Approach 1:
By applying local quality, the patent enables enhanced threshold voltage control specifically at the gate area without proportionally increasing the overall transistor volume. The terminal area maintains a cross-sectional area optimized for current conduction, while only the gate area portion is sized to provide adequate threshold voltage control, thus avoiding unnecessary size increase.
3Adaptability or versatility
If the fin cross-sectional area is uniformly modified to adjust threshold voltage, then the threshold voltage changes, but the contact area between fin and gate is also affected, limiting independent optimization
Solution Approach 1:
The segmentation of the fin into gate area and terminal area portions enables independent optimization of threshold voltage and contact area. The gate area cross-sectional area can be modified to control threshold voltage without affecting the terminal area contact dimensions, providing the manufacturing flexibility needed for independent parameter optimization.
Solution Approach 2:
By implementing local quality with different cross-sectional areas at different fin positions, the patent allows the gate area to be independently optimized for threshold voltage control while the terminal area maintains optimal contact area. This local differentiation enables independent parameter optimization that would not be possible with uniform fin dimensions.
Data Source
AI summary
Aspects of the present disclosure include finFET structures with varied cross-sectional areas and methods of forming the same. Methods according to the present disclosure can include, e.g., forming a structure including: a semiconductor fin positioned on a substrate, wherein the semiconductor fin includes: a gate area, and a terminal area laterally distal to the gate area, a sacrificial gate positioned on the gate area of the semiconductor fin, and an insulator positioned on the terminal area of the semiconductor fin; removing the sacrificial gate to expose the gate area of the semiconductor fin; increasing or reducing a cross-sectional area of the gate area of the semiconductor fin; and forming a transistor gate on the gate area of the semiconductor fin.