FinFET Gate Structure With Auxiliary Pattern for Channel Width
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Solution Overview
Problem
The scaling down of MOSFETs in semiconductor devices deteriorates their operating characteristics, necessitating improved methods for fabricating devices with superior performance and high integration.
Innovation Solution
The semiconductor device incorporates semiconductor patterns protruding perpendicularly from a substrate, with auxiliary patterns and gate dielectric layers extending over these patterns, and gate electrodes covering both, enhancing the effective channel width and channel characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If MOSFET sizes are scaled down to increase integration, then device density increases, but operating characteristics deteriorate
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional FinFET structures with vertical fins protruding from the substrate. This dimensional change increases the effective channel width without increasing the planar footprint, thereby improving integration density while maintaining or enhancing operating characteristics through better gate control of the channel.
Solution Approach 2:
The gate electrode structure wraps around the vertical fin structure in a nested configuration, with the gate dielectric layer and gate electrode enclosing the fin from multiple sides. This nested arrangement provides superior gate control compared to planar structures, improving carrier modulation while maintaining compact device dimensions for high integration.
2Reliability
If FinFET structures are implemented to improve channel characteristics, then effective channel width increases, but device complexity increases
Solution Approach 1:
The channel region is segmented into multiple vertical fin structures rather than using a single planar channel. Each fin acts as an independent channel segment with its own gate-controlled depletion region. This segmentation increases the total effective channel width and improves gate control while allowing modular fabrication through standard photolithography and etching processes.
Solution Approach 2:
The fin structures are pre-formed through selective epitaxial growth or deposition before gate electrode formation. This preliminary structuring of the channel region simplifies subsequent gate fabrication by providing well-defined vertical surfaces for gate dielectric deposition and gate electrode patterning, reducing overall process complexity despite the three-dimensional structure.
Data Source
AI summary
A semiconductor device includes a semiconductor pattern protruding in a direction perpendicular to a top surface of a substrate and having an inner surface and an outer surface that stand opposite to each other in a first direction parallel to the top surface of the substrate, a gate dielectric layer covering the inner surface and the outer surface of the semiconductor pattern and extending onto a top surface of the semiconductor pattern, a gate electrode on the gate dielectric layer and covering the outer surface, the top surface, and the inner surface of the semiconductor pattern, and an auxiliary pattern between the gate dielectric layer and the inner surface of the semiconductor pattern. The outer surface of the semiconductor pattern is in contact with the gate dielectric layer. The inner surface of the semiconductor pattern is in contact with the auxiliary pattern.