FinFET Gate Cap Structure for SiGe Interface Defect Control
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, challenges arise in integrating more components into a given area, including issues with interfacial defects and performance degradation, particularly when using materials like epitaxially grown silicon germanium, which can enhance carrier mobility but also affect other performance characteristics.
Innovation Solution
The process involves forming fin-like field-effect transistors (FinFETs) with a gate-last approach, using a series of steps including trench formation, dielectric filling, dummy gate creation, and metal cap layer formation, with specific etching and deposition techniques to manage the gate stack and cap layers, ensuring proper alignment and stressor formation for improved channel regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If epitaxially grown silicon germanium is used to enhance carrier mobility, then carrier mobility is improved, but interfacial defects increase
Solution Approach 1:
A silicon nitride layer is introduced as an intermediary between the silicon germanium channel and the metal gate electrode. This intermediate layer acts as a buffer that reduces interfacial defects and prevents direct interaction between the high-stress silicon germanium and the metal gate, thereby maintaining carrier mobility while reducing interface-related performance degradation.
Solution Approach 2:
The gate structure employs a composite material approach by combining multiple layers including silicon nitride and metal cap layers. This composite structure allows optimization of each layer's properties - the silicon nitride provides interface protection while the metal cap provides electrical functionality, collectively solving both the mobility enhancement and defect reduction requirements.
2Productivity
If minimum feature size is reduced to increase integration density, then integration density is improved, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
The silicon nitride layer is formed preliminarily before metal gate deposition, creating a stable interface structure in advance. This preliminary action establishes a controlled foundation that reduces variability in subsequent processing steps, enabling better feature size control even as dimensions are reduced to increase integration density.
Solution Approach 2:
The invention changes the interface material parameters by introducing silicon nitride with specific dielectric and mechanical properties. This parameter change creates a more stable interface that is less sensitive to dimensional variations, allowing manufacturing precision to be maintained at smaller feature sizes required for higher integration density.
3Reliability
If metal cap layer is formed over gate stack, then gate control is improved, but process complexity increases
Solution Approach 1:
The gate structure is segmented into distinct functional layers: the silicon nitride layer handles interface protection and stress management, while the metal cap layer provides electrical gate control. This segmentation allows each layer to be optimized independently and formed using standard deposition processes, improving gate control without proportionally increasing overall process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances integration density and performance by reducing interfacial defects and optimizing carrier mobility, while maintaining control over stressor formation and dopant implantation, leading to improved semiconductor device performance.
Implementation Method 1
The etch solution selectively removes the sacrificial oxide layer
Implementation Method 2
depositing insulating or dielectric layers, conductive layers, and semiconductor layers
Implementation Method 3
depositing insulating or dielectric layers, conductive layers, and semiconductor layers
Implementation Method 4
dopant implantation
Data Source
AI summary
Disclosed is a semiconductor fabrication method. The method includes forming a gate stack in an area previously occupied by a dummy gate structure; forming a first metal cap layer over the gate stack; forming a first dielectric cap layer over the first metal cap layer; selectively removing a portion of the gate stack and the first metal cap layer while leaving a sidewall portion of the first metal cap layer that extends along a sidewall of the first dielectric cap layer; forming a second metal cap layer over the gate stack and the first metal cap layer wherein a sidewall portion of the second metal cap layer extends further along a sidewall of the first dielectric cap layer; forming a second dielectric cap layer over the second metal cap layer; and flattening a top layer of the first dielectric cap layer and the second dielectric cap layer using planarization operations.