FinFET Gate Capacitance Reduction via Backside Etching
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Solution Overview
Problem
FinFET transistors face performance limitations due to excess gate material, which increases gate capacitance, leading to higher power consumption and reduced switching rates.
Innovation Solution
A method for removing excess gate material through backside wafer processing, resulting in T-shaped gates with a narrower portion closer to the spacer and a wider portion further away, reducing parasitic capacitance and improving transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If excess gate material is present in FinFET transistors, then the gate structure is more complete and easier to manufacture, but gate capacitance increases leading to higher power consumption and reduced switching rates
Solution Approach 1:
The patent applies the extraction principle by selectively removing excess gate material from the FinFET structure. The method involves etching away portions of the gate material that extend beyond the source and drain regions, thereby reducing parasitic capacitance while maintaining the essential gate structure needed for transistor operation. This extraction of unnecessary material directly addresses the contradiction by eliminating the source of excess capacitance without compromising the fundamental gate structure.
Solution Approach 2:
The patent implements local quality by creating a non-uniform gate structure where the gate material width varies along its length. Specifically, the gate material is narrower at the ends adjacent to source/drain regions compared to the center portion. This local variation in gate dimensions allows the structure to have different properties in different regions: sufficient width in the center for strong control and reduced width at ends for lower parasitic capacitance, thus resolving the contradiction between complete structure and reduced energy consumption.
2Ease of manufacture
If excess gate material is present in FinFET transistors, then the gate structure is more complete and easier to manufacture, but switching rates are reduced due to increased gate capacitance
Solution Approach 1:
The patent applies the extraction principle by selectively removing excess gate material from the FinFET structure. The method involves etching away portions of the gate material that extend beyond the source and drain regions, thereby reducing parasitic capacitance while maintaining the essential gate structure needed for transistor operation. This extraction of unnecessary material directly addresses the contradiction by eliminating the source of excess capacitance without compromising the fundamental gate structure.
Solution Approach 2:
The patent implements local quality by creating a non-uniform gate structure where the gate material width varies along its length. Specifically, the gate material is narrower at the ends adjacent to source/drain regions compared to the center portion. This local variation in gate dimensions allows the structure to have different properties in different regions: sufficient width in the center for strong control and reduced width at ends for lower parasitic capacitance, thus resolving the contradiction between complete structure and reduced energy consumption.
3Use of energy by moving object
If gate material is reduced to remove excess portions, then gate capacitance and power consumption decrease, but the gate structure becomes more complex requiring additional processing steps
Solution Approach 1:
The patent applies preliminary action by performing the gate material removal during the existing fabrication sequence at an optimal point in the process. The excess gate material is etched away after the gate structure is formed but before subsequent processing steps that would require precise alignment. This timing allows the modification to be integrated into the existing manufacturing flow with minimal additional complexity, as the gate structure is already in place and subsequent steps are not yet constrained by the presence of excess material.
Data Source
AI summary
The disclosure illustrates systems and methods for removing at least some excess gate material of a FinFET transistor. A FinFET transistor with the excess gate material removed may include a gate with a T-shaped cross-section. The narrower portion of the cross-section may be processed using backside wafer processing. The width of the narrower portion may be defined by a spacer.