FinFET Gate Line Segmentation for Parasitic Capacitance Reduction
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Solution Overview
Problem
As IC devices become more integrated and gate lengths of field effect transistors (FETs) are reduced, there is a need to improve operation speed and reduce power consumption by minimizing parasitic capacitance, which existing technologies have not adequately addressed.
Innovation Solution
The integration circuit (IC) device design includes a substrate with fin-type active regions and deep trench regions, featuring a gate line with distinct portions of different thicknesses and levels, along with insulating layers and spacers to reduce parasitic capacitance, and a manufacturing method that forms these structures to achieve improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If gate length is reduced to improve integration, then device integration increases, but parasitic capacitance increases and operation speed decreases
Solution Approach 1:
The gate line is divided into two distinct portions: a first gate portion with greater thickness positioned over the fin-type active region, and a second gate portion with smaller thickness positioned over the deep trench region. This segmentation allows different gate thicknesses in different spatial zones, reducing parasitic capacitance in the deep trench area while maintaining effective gating over the active region, thereby preserving operation speed despite reduced gate lengths.
2Productivity
If gate length is reduced to improve integration, then device integration increases, but power consumption increases due to parasitic capacitance
Solution Approach 1:
The gate line is divided into two distinct portions: a first gate portion with greater thickness positioned over the fin-type active region, and a second gate portion with smaller thickness positioned over the deep trench region. This segmentation allows different gate thicknesses in different spatial zones, reducing parasitic capacitance in the deep trench area while maintaining effective gating over the active region, thereby preserving operation speed despite reduced gate lengths.
3Ease of manufacture
If uniform gate thickness is used, then manufacturing is simpler, but parasitic capacitance cannot be minimized
Solution Approach 1:
The gate line exhibits non-uniform thickness with a first gate portion having greater thickness over the fin-type active region and a second gate portion having smaller thickness over the deep trench region. This local quality variation optimizes electrical characteristics by reducing parasitic capacitance in the deep trench area while maintaining effective gate control over the active region, demonstrating that localized structural differentiation resolves the contradiction between manufacturing simplicity and performance optimization.
4Object-affected harmful factors
If gate thickness is reduced to minimize parasitic capacitance, then parasitic capacitance decreases, but gate control over channel deteriorates
Solution Approach 1:
The gate line exhibits non-uniform thickness with a first gate portion having greater thickness over the fin-type active region and a second gate portion having smaller thickness over the deep trench region. This local quality variation optimizes electrical characteristics by reducing parasitic capacitance in the deep trench area while maintaining effective gate control over the active region, demonstrating that localized structural differentiation resolves the contradiction between manufacturing simplicity and performance optimization.
Data Source
AI summary
An IC device includes a substrate including a device region having a fin-type active region and a deep trench region; a gate line that extends in a direction intersecting the fin-type active region; and an inter-device isolation layer that fills the deep trench region. The gate line includes a first gate portion that extends on the device region to cover the fin-type active region and has a flat upper surface at a first level and a second gate portion that extends on the deep trench region to cover the inter-device isolation layer while being integrally connected to the first gate portion and has an upper surface at a second level that is closer to the substrate than the first level.