FinFET Gate Capping Layer for Etch Uniformity
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Solution Overview
Problem
Existing FinFET devices face challenges in controlling etch uniformity due to the loading effect, which affects the formation of gate structures with different widths, leading to height gaps and potential performance degradation.
Innovation Solution
The formation of a first capping layer over the wider gate structure to protect underlying layers during planarization processes, ensuring uniformity and preventing damage, while a second capping layer is selectively formed on the narrower gate structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single planarization process is applied to gate structures of different widths, then processing is simplified, but etch uniformity deteriorates due to the loading effect
Solution Approach 1:
The patent divides the gate structures into two groups based on width: wider gate structures and narrower gate structures. This segmentation allows each group to receive tailored planarization treatment, with the wider gates receiving additional capping layer protection and extended planarization to ensure uniform etching across all gate structures regardless of width differences.
Solution Approach 2:
The patent applies different planarization strategies to different regions: wider gate structures receive a capping layer and extended planarization treatment, while narrower gate structures receive standard planarization. This local quality approach ensures that each region receives the appropriate level of protection and processing to achieve uniform etching results.
2Manufacturing precision
If the wider gate structure is planarized to the same level as the narrower gate structure, then uniformity is improved, but the underlying layers of the wider gate may be damaged
Solution Approach 1:
The patent applies a capping layer to the wider gate structure before the planarization process. This preliminary action protects the underlying layers of the wider gate from damage during the extended planarization process, allowing the wider gate to be planarized to the same level as narrower gates without compromising layer integrity.
Solution Approach 2:
The capping layer serves as a cushioning layer that absorbs the mechanical stress and potential damage from the planarization process. By placing this protective layer beforehand on the wider gate structure, the patent prevents direct damage to the underlying sensitive layers during the extended planarization required to achieve uniform height across all gate structures.
3Manufacturing precision
If selective capping layers are formed on different gate structures, then etch uniformity is improved, but fabrication complexity increases
Solution Approach 1:
The patent changes the physical parameters of the wider gate structures by adding a capping layer with specific material properties and thickness. This parameter change enables the wider gates to withstand extended planarization without damage, achieving uniform etching across all gate structures. The complexity is managed by focusing the selective treatment only on wider gates rather than all gates.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the uniformity of etching and prevents performance degradation by protecting the wider gate structure, reducing fabrication time and costs, and maintaining the integrity of the FinFET device.
Implementation Method 1
The formation of a first capping layer over the wider gate structure to protect underlying layers during planarization processes, ensuring uniformity and preventing damage
Data Source
AI summary
A FinFET device structure is provided. The FinFET device structure includes a first gate structure formed over a fin structure, and a conductive layer formed over the first gate structure. The FinFET device structure includes a first capping layer formed over the conductive layer, and a top surface of the conductive layer is in direct contact with a bottom surface of the first capping layer.