FinFET Gate Capping Structure Against Metal Seam Etching Loss
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Solution Overview
Problem
As semiconductor devices become highly integrated with decreasing channel lengths, seams may form near gate metal filling films, leading to chemical penetration during etching, which can result in the loss of work function metals and shifts in operating voltage, ultimately affecting device parameters and yield.
Innovation Solution
The semiconductor device incorporates a fin-type pattern with a gate electrode extending in a different direction, featuring spacers, a capping structure with multiple layers including conductive and insulating materials, and an interlayer insulating film surrounding these components to prevent chemical penetration and enhance structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor devices are highly integrated with decreasing channel lengths, then device integration and scaling are improved, but seams form near gate metal filling films leading to chemical penetration and loss of work function metals
Solution Approach 1:
The gate electrode structure is segmented into multiple functional layers: a gate electrode layer providing electrical function, a first capping pattern layer (conductive material) preventing chemical penetration, and a second capping pattern layer (insulating material) providing additional protection. This segmentation allows each layer to address specific requirements, preventing seam formation while maintaining device integration.
Solution Approach 2:
The gate electrode structure uses composite materials with different properties: conductive materials (tungsten, cobalt, copper) for electrical function, and insulating materials (silicon nitride, silicon oxide) for chemical protection. This composite structure prevents chemical penetration through seams while maintaining the electrical functionality required for high device integration.
2Reliability
If seams form near gate metal filling films, then chemical penetration occurs during etching, but the capping structure with multiple layers prevents this penetration
Solution Approach 1:
The protective capping structure is divided into two distinct patterned layers: a first capping pattern layer made of conductive material and a second capping pattern layer made of insulating material. Each layer provides specific protection functions, and their segmented structure allows precise control over chemical penetration paths during etching processes.
Solution Approach 2:
The first capping pattern layer acts as an intermediary between the gate electrode layer and the second capping pattern layer. It provides initial chemical protection while allowing the structure to maintain electrical connectivity, and the second layer provides additional protection. This intermediary structure prevents direct chemical exposure to work function metals.
3Reliability
If the interlayer insulating film surrounds sidewalls of spacers and capping structure, then chemical penetration is prevented, but manufacturing complexity increases
Solution Approach 1:
The interlayer insulating film is formed preliminarily to surround the sidewalls of spacers and capping structures before subsequent processing steps. This preliminary protective action prevents chemical penetration during etching and other fabrication processes, ensuring structural integrity is maintained throughout manufacturing.
Solution Approach 2:
The interlayer insulating film acts as a flexible protective shell surrounding the rigid capping structures and spacers. This thin film provides chemical protection while accommodating the complex three-dimensional geometry of the underlying structures, maintaining structural integrity without requiring rigid encapsulation.
Data Source
AI summary
A semiconductor device and a method of fabricating a semiconductor device, the device including a fin-type pattern extending in a first direction; a gate electrode extending in a second direction over the fin-type pattern, the second direction being different from the first direction; spacers on sidewalls of the gate electrode; a capping structure on the gate electrode and the spacers, the capping structure including a first capping pattern and a second capping pattern, the second capping pattern being on the first capping pattern; and an interlayer insulating film surrounding sidewalls of each of the spacers and sidewalls of the capping structure, the interlayer insulating film being in contact with the first capping pattern.