FinFET Gate Structure With Capping Layer for Uniform Scaling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in integrated circuit device manufacturing is to maintain uniformity and efficiency as line widths and pitches decrease with down-scaling, requiring precise formation of components to achieve fast operating speeds and accurate operations.
Innovation Solution
The proposed integrated circuit device structure includes a fin-type active area, a stopper layer, a gate electrode, and a gate capping layer, with a gate insulating layer and spacers, where the gate electrodes have recesses on their upper surfaces and are positioned between the fin-type active areas and stoppers, allowing for precise control of dimensions and improved manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If down-scaling of integrated circuit device is performed to reduce line widths and pitches, then device integration density is improved, but manufacturing precision deteriorates due to difficulty in uniformly forming components
Solution Approach 1:
The gate capping layer is formed in advance to cover the gate electrode before subsequent processing steps. This preliminary action protects the gate electrode structure and enables precise formation of the gate electrode pattern, allowing uniform component formation even at reduced line widths and pitches.
Solution Approach 2:
The gate capping layer serves as an intermediary structure between the gate electrode and the surrounding components (stopper layer, gate spacer). It mediates the formation process by providing a defined interface that facilitates uniform patterning and dimensional control of adjacent structures during down-scaling.
2Speed
If gate electrode height is reduced to improve AC characteristics, then device performance is improved, but manufacturing precision deteriorates due to difficulty in maintaining uniform structure
Solution Approach 1:
The gate capping layer is formed as a copy or extension of the gate electrode structure, covering it completely. This copying approach transfers the dimensional control from the gate electrode formation step to the capping layer formation step, enabling precise control of gate electrode height and uniformity even when the height is reduced for improved AC characteristics.
3Volume of moving object
If line widths and pitches are reduced for down-scaling, then device miniaturization is achieved, but reliability deteriorates due to increased variability in component formation
Solution Approach 1:
The gate capping layer provides localized coverage and protection to the gate electrode structure. This local quality enhancement at the gate region ensures uniform formation and dimensional control of critical components, maintaining reliability even as overall device size is reduced through down-scaling of line widths and pitches.
Data Source
AI summary
An integrated circuit device according to the inventive concept includes: a fin-type active area protruding from a substrate and extending in a first horizontal direction; a stopper layer that is above and spaced apart from the fin-type active area; a gate electrode extending in a second horizontal direction orthogonal to the first horizontal direction, on the fin-type active area, and in a space between the fin-type active area and the stopper layer; and a gate capping layer on upper surfaces of the gate electrode and the stopper layer.