FinFET Replacement Gate Layout for Critical Dimension Control
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Solution Overview
Problem
Existing technologies for forming replacement gates in FinFET devices face issues with undesirable lateral etching, leading to reduced critical dimensions due to high and less controllable etching rates, especially in sparse areas where dummy gate structures are formed, resulting in opposite-pointing tip edges.
Innovation Solution
The method involves patterning blanket dummy gate structures with different profiles in dense and sparse areas, using intermediate dummy gates with specific recess angles to ensure that adjacent dummy gate structures have tip edges pointing towards each other, maintaining critical dimensions by controlling etching and passivation processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional etching processes are used to form dummy gate structures, then manufacturing simplicity is maintained, but lateral etching occurs at the bottom portions causing reduced critical dimensions and misaligned tip edges
Solution Approach 1:
The patent applies different etching processes to different regions of the dummy gate structures based on their location and function. High-density area dummy gates receive one etching treatment while low-density area dummy gates receive another, allowing each region to achieve the desired tip edge alignment and critical dimension control without requiring complex universal processes
Solution Approach 2:
The patent segments the dummy gate structures into multiple types based on their location (high-density vs. low-density areas) and forms them with different profiles. This segmentation allows tailored etching processes for each segment, preventing lateral etching issues while maintaining manufacturing feasibility
2Device complexity
If blanket dummy gate structures are patterned uniformly, then process simplicity is maintained, but critical dimensions are reduced and tip edges become misaligned in areas with varying transistor densities
Solution Approach 1:
The patent implements local quality by creating different dummy gate profiles for high-density and low-density areas. The high-density area dummy gates have one profile configuration while low-density area dummy gates have another, allowing precise control of critical dimensions and tip edge alignment in each specific region
Solution Approach 2:
The patent segments the uniform blanket dummy gate structure into multiple differentiated profiles based on transistor density regions. This segmentation enables tailored patterning processes that maintain critical dimension accuracy and tip edge alignment while managing device complexity through systematic classification
3Ease of manufacture
If tip edges of adjacent dummy gates are allowed to point in different directions, then manufacturing is simplified, but critical dimensions are reduced and alignment accuracy deteriorates
Solution Approach 1:
The patent applies preliminary action by carefully designing and forming the dummy gate structures with tip edges that point toward each other before subsequent processing steps. This preliminary configuration ensures accurate alignment and critical dimension maintenance while simplifying later manufacturing steps by preventing alignment issues before they arise
Data Source
AI summary
A semiconductor device includes a substrate. The semiconductor device includes a fin that is formed over the substrate and extends along a first direction. The semiconductor device includes a gate structure that straddles the fin and extends along a second direction perpendicular to the first direction. The semiconductor device includes a first source/drain structure coupled to a first end of the fin along the first direction. The gate structure includes a first portion protruding toward the first source/drain structure along the first direction. A tip edge of the first protruded portion is vertically above a bottom surface of the gate structure.